URL
https://opencores.org/ocsvn/mips32r1/mips32r1/trunk
Show entire file |
Details |
Blame |
View Log
Rev 3 |
Rev 12 |
Line 27... |
Line 27... |
// 100MHz / (2^17 / 151) == 115203.857 Hz
|
// 100MHz / (2^17 / 151) == 115203.857 Hz
|
// 66MHz / (2^14 / 453) == 16 * 115203.857 Hz
|
// 66MHz / (2^14 / 453) == 16 * 115203.857 Hz
|
// 66MHz / (2^18 / 453) == 115203.857 Hz
|
// 66MHz / (2^18 / 453) == 115203.857 Hz
|
|
|
|
|
|
// 66 MHz version
|
|
reg [14:0] accumulator = 15'h0000;
|
|
always @(posedge clock) begin
|
|
accumulator <= accumulator[13:0] + 453;
|
|
end
|
|
assign uart_tick_16x = accumulator[14];
|
|
|
/*
|
/*
|
// 66 MHz version
|
// 100 MHz version
|
reg [14:0] accumulator = 15'h0000;
|
reg [13:0] accumulator = 14'h0000;
|
always @(posedge clock) begin
|
always @(posedge clock) begin
|
accumulator <= accumulator[13:0] + 453;
|
accumulator <= accumulator[12:0] + 151;
|
end
|
end
|
assign uart_tick_16x = accumulator[14];
|
assign uart_tick_16x = accumulator[13];
|
*/
|
*/
|
|
|
// 100 MHz version
|
|
reg [13:0] accumulator = 14'h0000;
|
|
always @(posedge clock) begin
|
|
accumulator <= accumulator[12:0] + 151;
|
|
end
|
|
assign uart_tick_16x = accumulator[13];
|
|
|
|
|
|
//------------------------------
|
//------------------------------
|
reg [3:0] uart_16x_count = 4'h0;
|
reg [3:0] uart_16x_count = 4'h0;
|
always @(posedge clock) begin
|
always @(posedge clock) begin
|
uart_16x_count <= (uart_tick_16x) ? uart_16x_count + 1 : uart_16x_count;
|
uart_16x_count <= (uart_tick_16x) ? uart_16x_count + 1 : uart_16x_count;
|
end
|
end
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.