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`include "include.h"
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/******************************************************************
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* *
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* Author: Liwei *
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* *
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* This file is part of the "mips789" project. *
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* Downloaded from: *
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* http://www.opencores.org/pdownloads.cgi/list/mips789 *
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* *
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* If you encountered any problem, please contact me via *
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* Email:mcupro@opencores.org or mcupro@163.com *
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* *
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******************************************************************/
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`include "mips789_defs.v"
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module ctl_FSM (
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module ctl_FSM (
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clk, iack, id2ra_ctl_clr, id2ra_ctl_cls,
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clk, iack, id2ra_ctl_clr, id2ra_ctl_cls,
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id2ra_ins_clr, id2ra_ins_cls, id_cmd, irq,
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id2ra_ins_clr, id2ra_ins_cls, id_cmd, irq,
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pc_prectl, ra2exec_ctl_clr, rst ,zz_is_nop
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pc_prectl, ra2exec_ctl_clr, rst ,zz_is_nop
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);
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);
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wire rst;
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wire rst;
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reg riack;
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reg riack;
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reg [5:0]delay_counter_Sreg0, next_delay_counter_Sreg0;
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reg [5:0]delay_counter_Sreg0, next_delay_counter_Sreg0;
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reg [3:0] CurrState_Sreg0;
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reg [3:0] CurrState_Sreg0;
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reg [3:0] NextState_Sreg0;
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reg [3:0] NextState_Sreg0;
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always @ (*)
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always @ (*)
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begin : Sreg0_NextState
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begin : Sreg0_NextState
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case (CurrState_Sreg0) // synopsys parallel_case full_case
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case (CurrState_Sreg0)
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`IDLE:
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`IDLE:
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begin
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begin
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id2ra_ins_clr=ZERO;
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id2ra_ins_clr=ZERO;
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id2ra_ins_cls=ZERO;
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id2ra_ins_cls=ZERO;
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id2ra_ctl_clr=ZERO;
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id2ra_ctl_clr=ZERO;
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riack=ZERO;
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riack=ZERO;
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if (~rst)
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if (~rst)
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NextState_Sreg0 = `RST;
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NextState_Sreg0 = `RST;
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else
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else
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NextState_Sreg0 = `IDLE;
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NextState_Sreg0 = `IDLE;
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end
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end
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`LD:
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`LD:
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begin
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begin
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id2ra_ins_clr=ONE;
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id2ra_ins_clr=ONE;
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id2ra_ins_cls=ZERO;
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id2ra_ins_cls=ZERO;
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if (delay_counter_Sreg0 == 0)
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if (delay_counter_Sreg0 == 0)
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NextState_Sreg0 = `IDLE;
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NextState_Sreg0 = `IDLE;
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else
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else
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begin
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begin
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NextState_Sreg0 = `D2_MUL_DLY;
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NextState_Sreg0 = `D2_MUL_DLY;
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if (delay_counter_Sreg0 != 0)
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// if (delay_counter_Sreg0 != 0)
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next_delay_counter_Sreg0 = delay_counter_Sreg0 - 1;
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next_delay_counter_Sreg0 = delay_counter_Sreg0 - 1;
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end
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end
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end
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end
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default : //the same as RST
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default : //the same as RST
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end
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end
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endcase
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endcase
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end
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end
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always @ (posedge clk/* or negedge rst*/)
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always @ (posedge clk)
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begin : Sreg0_CurrentState
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begin : Sreg0_CurrentState
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if (~rst)
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if (~rst)
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CurrState_Sreg0 <= `RST;
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CurrState_Sreg0 <= `RST;
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else
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else
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CurrState_Sreg0 <= NextState_Sreg0;
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CurrState_Sreg0 <= NextState_Sreg0;
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end
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end
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always @ (posedge clk /*or negedge rst*/)
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always @ (posedge clk )
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begin : Sreg0_RegOutput
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begin : Sreg0_RegOutput
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if (~rst)
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if (~rst)
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begin
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begin
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delay_counter_Sreg0 <= 40 ; // Initialization in the reset state or default value required!!
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delay_counter_Sreg0 <= 40 ; // Initialization in the reset state or default value required!!
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end
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end
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