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`include "include.h"
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/******************************************************************
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* *
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* Author: Liwei *
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* *
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* This file is part of the "mips789" project. *
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* Downloaded from: *
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* http://www.opencores.org/pdownloads.cgi/list/mips789 *
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* *
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* If you encountered any problem, please contact me via *
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* Email:mcupro@opencores.org or mcupro@163.com *
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* *
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******************************************************************/
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`include "mips789_defs.v"
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module rxd_d(input clr,input clk,input d,output reg q );
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module rxd_d(input clr,input clk,input d,output reg q );
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always @(posedge clk or posedge clr)
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always @(posedge clk)
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if (clr) q<=0;
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if (clr) q<=0;
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else q<=d|q;
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else q<=d|q;
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endmodule
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endmodule
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output [7:0] dout;
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output [7:0] dout;
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wire [7:0] dout;
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wire [7:0] dout;
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wire clk_uart=clk;
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wire clk_uart=clk;
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wire w_rxd_rdy;
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wire w_rxd_rdy;
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wire w_rxd_clr;
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uart_read uart_rd_tak(
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uart_read uart_rd_tak(
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.sync_reset(rst),
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.sync_reset(rst),
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.clk(clk),
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.clk(clk),
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.rxd(ser_rxd),
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.rxd(ser_rxd),
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.write_busy(txd_busy)
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.write_busy(txd_busy)
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);
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);
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endmodule
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endmodule
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//These modules below are modified slight by Liwei based on YACC,an CPU core in opencores.
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//Thank you TAK
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module uart_write( sync_reset, clk, txd, data_in , write_request,write_done,write_busy);
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module uart_write( sync_reset, clk, txd, data_in , write_request,write_done,write_busy);
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input sync_reset,clk;
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input sync_reset,clk;
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input [7:0] data_in;
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input [7:0] data_in;
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input write_request;
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input write_request;
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//________|--|___write_request (upper module : its period should be 1clock time.)
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//________|--|___write_request (upper module : its period should be 1clock time.)
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//__________________________|-|______write_done (Responds by this module posedge interrupt)
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//__________________________|-|______write_done (Responds by this module posedge interrupt)
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//With 512Bytes FIFO.
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//With 512Bytes FIFO.
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//No error handling is supported.
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//No error handling is supported.
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reg [15:0] clk_ctr;
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reg [15:0] clk_ctr;//liwei
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reg [2:0] bit_ctr;
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reg [2:0] bit_ctr;
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reg [2:0] ua_state;
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reg [2:0] ua_state;
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reg [7:0] tx_sr;
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reg [7:0] tx_sr;
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reg write_done_n;
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reg txd;
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reg txd;
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wire clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7,
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wire clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7,
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clk_ctr_enable_state, bit_ctr_enable_state ;
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clk_ctr_enable_state, bit_ctr_enable_state ;
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wire tx_state;
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wire tx_state;
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assign read_request = queing && ua_state==3'b000;//Jul.14.2004
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assign read_request = queing && ua_state==3'b000;//Jul.14.2004
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assign write_done=ua_state==3'b101;
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assign write_done=ua_state==3'b101;
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`ifdef ALTERA
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`ifdef ALTERA
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fifo512_cyclone fifo(
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fifo512_cyclone alt_fifo(
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.data(data_in),
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.data(data_in),
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.wrreq(write_request),
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.wrreq(write_request),
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.rdreq(read_request),
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.rdreq(read_request),
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.clock(clk),
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.clock(clk),
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.q(queue_data),
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.q(queue_data),
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.full(queue_full),
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.full(queue_full),
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.empty(empty));
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.empty(empty));
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`else//XILINX coregen
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`else//debug model in simulations
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fifo fifo(
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sim_fifo512_cyclone sim_fifo(
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.clk(clk),
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.data(data_in),
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.sinit(sync_reset),
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.wrreq(write_request),
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.din(data_in),
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.rdreq(read_request),
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.wr_en(write_request),
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.clock(clk),
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.rd_en(read_request),
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.q(queue_data),
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.dout(queue_data),
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.full(queue_full),
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.full(queue_full),
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.empty(empty));
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.empty(empty),
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.rst(sync_reset));
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`endif
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`endif
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// 7bit counter
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// 7bit counter
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// I set the regerster lenth as 16 .Sufficent but not waste.Liwei
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (~sync_reset)
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if (~sync_reset)
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clk_ctr <= 0;
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clk_ctr <= 0;
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else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0;
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else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0;
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else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1;
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else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1;
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3'b000: if (queing) ua_state <= 3'b001; //wait write_request
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3'b000: if (queing) ua_state <= 3'b001; //wait write_request
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3'b001: if ( clk_ctr_equ15) ua_state <= 3'b010; // write start bit
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3'b001: if ( clk_ctr_equ15) ua_state <= 3'b010; // write start bit
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3'b010: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'b011; // start bit, bit0-7 data send
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3'b010: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'b011; // start bit, bit0-7 data send
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3'b011: if (clk_ctr_equ15) ua_state <= 3'b100; // bit7 data send
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3'b011: if (clk_ctr_equ15) ua_state <= 3'b100; // bit7 data send
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3'b100: if (clk_ctr_equ15) ua_state <= 3'b101; // stop bit // stop bit send
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3'b100: if (clk_ctr_equ15) ua_state <= 3'b101; // stop bit // stop bit send
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3'b101: if (clk_ctr_equ15) ua_state <= 3'b110; //LIWEI // stop bit // stop bit send
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3'b101: if (clk_ctr_equ15) ua_state <= 3'b110; //LIWEI // stop bit send
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3'b110: if (clk_ctr_equ15) ua_state <= 3'b111; //LIWEI
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3'b110: if (clk_ctr_equ15) ua_state <= 3'b111; //LIWEI
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3'b111: ua_state <= 3'h0; // TAK // byte read cycle end
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3'b111: ua_state <= 3'h0; // TAK // byte read cycle end
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default: ua_state <= 3'h0;
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default: ua_state <= 3'h0;
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endcase
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endcase
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end
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end
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assign clk_ctr_enable_state = ua_state !=3'b000 && ua_state<=3'b011;
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assign clk_ctr_enable_state = ua_state !=3'b000 && ua_state<=3'b011;
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assign bit_ctr_enable_state = ua_state==3'h2;
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assign bit_ctr_enable_state = ua_state==3'h2;
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//
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (~sync_reset) ua_state <= 3'h0;
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if (~sync_reset) ua_state <= 3'h0;
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else begin
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else begin
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case (ua_state)
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case (ua_state)
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3'h0: if (rxq1==0) ua_state <= 3'h1; // if rxd==0 then goto next state and enable clock // start bit search
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3'h0: if (rxq1==0) ua_state <= 3'h1; // if rxd==0 then goto next state and enable clock // start bit search
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end
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end
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//int_req
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//int_req
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (~sync_reset) int_req<=1'b0;
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if (~sync_reset) int_req<=1'b0;
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else if (ua_state==3'h4 ) int_req<=1'b1; //
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else if (ua_state==3'h4 ) int_req<=1'b1;
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else int_req<=1'b0;
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else int_req<=1'b0;
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end
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end
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// rx shift reg.
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// rx shift reg.
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