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[/] [mips789/] [tags/] [arelease/] [rtl/] [verilog/] [EXEC_stage.v] - Diff between revs 15 and 35

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Rev 15	Rev 35
Line 1...	Line 1...
`include "include.h"	`/******************************************************************`
	`* *`
	`* Author: Liwei *`
	`* *`
	`* This file is part of the "mips789" project. *`
	`* Downloaded from: *`
	`* http://www.opencores.org/pdownloads.cgi/list/mips789 *`
	`* *`
	`* If you encountered any problem, please contact me via *`
	`* Email:mcupro@opencores.org or mcupro@163.com *`
	`* *`
	`******************************************************************/`

	`include "mips789_defs.v"

`module exec_stage`	`module exec_stage`
`(`	`(`
`clk,rst,spc_cls_i,alu_func,`	`clk,rst,spc_cls_i,alu_func,`
`dmem_fw_ctl,ext_i,fw_alu,fw_dmem,`	`dmem_fw_ctl,ext_i,fw_alu,fw_dmem,`
Line 60...	Line 73...
`.clk(clk),`	`.clk(clk),`
`.ctl(alu_func),`	`.ctl(alu_func),`
`.rst(rst)`	`.rst(rst)`
`);`	`);`



`add32 add4`	`add32 add4`
`(`	`(`
`.d_i(pc_i),`	`.d_i(pc_i),`
`.d_o(BUS2446)`	`.d_o(BUS2446)`
`);`	`);`
Line 417...	Line 428...
`assign multiplicand=op1;`	`assign multiplicand=op1;`
`assign dividend=op1;`	`assign dividend=op1;`
`assign divider = op2;`	`assign divider = op2;`
assign sign = ((func==`ALU_MULT)\|\|(func==`ALU_DIV));	assign sign = ((func==`ALU_MULT)\|\|(func==`ALU_DIV));

	`initial`
	`begin`
	`hi=0;`
	`lo=0;`
	`end`
`always @( posedge clk /or negedge rst /)`	`always @( posedge clk /or negedge rst /)`
`if (~rst)`	`if (~rst)`
`begin`	`begin`
`mul_bit=0;`	`mul_bit=0;`
`div_bit=0;`	`div_bit=0;`
`hi = 0;`	`/*`
`lo = 0;`	`hi=0;`
	`lo=0;`
	`*/`
`negative_output = 0;`	`negative_output = 0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
if((ready)&&((func==`ALU_MULT)\|\|(func==`ALU_MULTTU)))	if((ready)&&((func==`ALU_MULT)\|\|(func==`ALU_MULTTU)))
Line 506...	Line 523...
`end`	`end`

`endmodule`	`endmodule`

`//creatied by Zhangfeifei`	`//creatied by Zhangfeifei`
`//modified ny Liwei`	`//modified by Liwei`
`module muldiv_ff`	`module muldiv_ff`
`(`	`(`
`clk_i,rst_i,`	`clk_i,rst_i,`
`op_type,op1,op2,`	`op_type,op1,op2,`
`rdy,res`	`rdy,res`
Line 558...	Line 575...
`reg finish;`	`reg finish;`
`reg add1; //if the quotient will add 1 at the end of the divide operation`	`reg add1; //if the quotient will add 1 at the end of the divide operation`
`reg addop2; //if the remainder will add op2 at the end of the divide operation`	`reg addop2; //if the remainder will add op2 at the end of the divide operation`
`reg addnop2;//if the remainder will add ~op2+1 at the end of the divide operation`	`reg addnop2;//if the remainder will add ~op2+1 at the end of the divide operation`


`always @( posedge clk_i /or negedge rst_i/)`	`always @( posedge clk_i /or negedge rst_i/)`
`begin`	`begin`
`if(~rst_i)`	`if(~rst_i)`
`begin`	`begin`
`count = 6'bx;`	`count = 6'bx;`

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[/] [mips789/] [tags/] [arelease/] [rtl/] [verilog/] [EXEC_stage.v] - Diff between revs 15 and 35