| Line 99... |
Line 99... |
wire tx_state;
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wire tx_state;
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wire empty;
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wire empty;
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assign write_busy=queue_full;//Apr.2.2005
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assign write_busy=queue_full;//Apr.2.2005
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always @ (posedge clk) begin
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always @ (posedge clk) begin
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if (sync_reset) read_request_ff<=1'b0;
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if (~sync_reset) read_request_ff<=1'b0;
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else read_request_ff<=read_request;
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else read_request_ff<=read_request;
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end
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end
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assign queing= !empty;
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assign queing= !empty;
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assign read_request = queing && ua_state==3'b000;//Jul.14.2004
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assign read_request = queing && ua_state==3'b000;//Jul.14.2004
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| Line 134... |
Line 134... |
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// 7bit counter
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// 7bit counter
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (sync_reset)
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if (~sync_reset)
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clk_ctr <= 0;
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clk_ctr <= 0;
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else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0;
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else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0;
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else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1;
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else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1;
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else clk_ctr <= 0;
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else clk_ctr <= 0;
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end
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end
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| Line 147... |
Line 147... |
assign clk_ctr_equ15 = clk_ctr==`COUNTER_VALUE1;
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assign clk_ctr_equ15 = clk_ctr==`COUNTER_VALUE1;
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assign clk_ctr_equ31 = clk_ctr==`COUNTER_VALUE2;
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assign clk_ctr_equ31 = clk_ctr==`COUNTER_VALUE2;
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// 3bit counter
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// 3bit counter
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (sync_reset)
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if (~sync_reset)
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bit_ctr <= 0;
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bit_ctr <= 0;
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else if (bit_ctr_enable_state) begin
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else if (bit_ctr_enable_state) begin
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if (clk_ctr_equ15)
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if (clk_ctr_equ15)
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bit_ctr <= bit_ctr + 1;
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bit_ctr <= bit_ctr + 1;
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end
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end
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| Line 164... |
Line 164... |
assign clk_ctr_enable_state = bit_ctr_enable_state ||ua_state==3'b110 || ua_state==3'b001 || ua_state==3'b100||ua_state==3'b101;
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assign clk_ctr_enable_state = bit_ctr_enable_state ||ua_state==3'b110 || ua_state==3'b001 || ua_state==3'b100||ua_state==3'b101;
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assign bit_ctr_enable_state = ua_state==3'b010 || ua_state==3'b011;
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assign bit_ctr_enable_state = ua_state==3'b010 || ua_state==3'b011;
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (sync_reset) ua_state <= 3'b000;
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if (~sync_reset) ua_state <= 3'b000;
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else begin
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else begin
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case (ua_state)
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case (ua_state)
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3'b000: if (queing) ua_state <= 3'b001; //wait write_request
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3'b000: if (queing) ua_state <= 3'b001; //wait write_request
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3'b001: if ( clk_ctr_equ15) ua_state <= 3'b010; // write start bit
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3'b001: if ( clk_ctr_equ15) ua_state <= 3'b010; // write start bit
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3'b010: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'b011; // start bit, bit0-7 data send
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3'b010: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'b011; // start bit, bit0-7 data send
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| Line 185... |
Line 185... |
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// tx shift reg.
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// tx shift reg.
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (sync_reset) tx_sr<=0;
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if (~sync_reset) tx_sr<=0;
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else if (read_request_ff) tx_sr <= queue_data[7:0]; //data_in[7:0]; // load
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else if (read_request_ff) tx_sr <= queue_data[7:0]; //data_in[7:0]; // load
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else if (tx_state ) tx_sr <= {1'b0, tx_sr[7:1]};
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else if (tx_state ) tx_sr <= {1'b0, tx_sr[7:1]};
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end
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end
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assign tx_state=( ua_state==3'h2 || ua_state==3'h3) && clk_ctr_equ15;
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assign tx_state=( ua_state==3'h2 || ua_state==3'h3) && clk_ctr_equ15;
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// tx
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// tx
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (sync_reset) txd <=1'b1;
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if (~sync_reset) txd <=1'b1;
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else if (sync_reset) txd<=1'b1;
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else if (~sync_reset) txd<=1'b1;
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else if (ua_state==3'h0) txd<=1'b1;
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else if (ua_state==3'h0) txd<=1'b1;
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else if (ua_state==3'h1 && clk_ctr_equ15) txd<=1'b0; // start bit
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else if (ua_state==3'h1 && clk_ctr_equ15) txd<=1'b0; // start bit
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else if (ua_state==3'h2 && clk_ctr_equ15) txd<=tx_sr[0];
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else if (ua_state==3'h2 && clk_ctr_equ15) txd<=tx_sr[0];
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else if (ua_state==3'h3 && clk_ctr_equ15) txd<=1'b1; // stop bit
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else if (ua_state==3'h3 && clk_ctr_equ15) txd<=1'b1; // stop bit
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end
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end
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| Line 239... |
Line 239... |
rxq1 <=rxd ;
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rxq1 <=rxd ;
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end
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end
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// 7bit counter
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// 7bit counter
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (sync_reset)
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if (~sync_reset)
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clk_ctr <= 0;
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clk_ctr <= 0;
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else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0;
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else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0;
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else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1;
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else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1;
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else clk_ctr <= 0;
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else clk_ctr <= 0;
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end
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end
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| Line 252... |
Line 252... |
assign clk_ctr_equ0= (clk_ctr==`COUNTER_VALUE3); //
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assign clk_ctr_equ0= (clk_ctr==`COUNTER_VALUE3); //
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// 3bit counter
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// 3bit counter
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (sync_reset)
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if (~sync_reset)
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bit_ctr <= 0;
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bit_ctr <= 0;
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else if (bit_ctr_enable_state) begin
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else if (bit_ctr_enable_state) begin
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if (clk_ctr_equ15)
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if (clk_ctr_equ15)
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bit_ctr <= bit_ctr + 1;
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bit_ctr <= bit_ctr + 1;
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end
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end
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| Line 270... |
Line 270... |
assign clk_ctr_enable_state = ua_state !=3'b000 && ua_state<=3'b011;
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assign clk_ctr_enable_state = ua_state !=3'b000 && ua_state<=3'b011;
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assign bit_ctr_enable_state = ua_state==3'h2;
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assign bit_ctr_enable_state = ua_state==3'h2;
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//
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//
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (sync_reset) ua_state <= 3'h0;
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if (~sync_reset) ua_state <= 3'h0;
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else begin
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else begin
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case (ua_state)
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case (ua_state)
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3'h0: if (rxq1==0) ua_state <= 3'h1; // if rxd==0 then goto next state and enable clock // start bit search
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3'h0: if (rxq1==0) ua_state <= 3'h1; // if rxd==0 then goto next state and enable clock // start bit search
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3'h1: if (clk_ctr_equ15) ua_state <= 3'h2; // start bit receive
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3'h1: if (clk_ctr_equ15) ua_state <= 3'h2; // start bit receive
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3'h2: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'h3;
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3'h2: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'h3;
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| Line 286... |
Line 286... |
end
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end
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//reg_we
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//reg_we
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (sync_reset) buffer_reg<=8'h00;
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if (~sync_reset) buffer_reg<=8'h00;
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else if (ua_state==3'h3 && clk_ctr_equ0) buffer_reg<=rx_sr;
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else if (ua_state==3'h3 && clk_ctr_equ0) buffer_reg<=rx_sr;
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end
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end
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//int_req
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//int_req
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (sync_reset) int_req<=1'b0;
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if (~sync_reset) int_req<=1'b0;
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else if (ua_state==3'h4 ) int_req<=1'b1; //
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else if (ua_state==3'h4 ) int_req<=1'b1; //
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else int_req<=1'b0;
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else int_req<=1'b0;
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end
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end
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// rx shift reg.
|
// rx shift reg.
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always @(posedge clk ) begin
|
always @(posedge clk ) begin
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if (sync_reset) rx_sr <= 0;
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if (~sync_reset) rx_sr <= 0;
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else if (clk_ctr_equ15) rx_sr <= {rxq1, rx_sr[7:1]};
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else if (clk_ctr_equ15) rx_sr <= {rxq1, rx_sr[7:1]};
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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