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`include "include.h"
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/******************************************************************
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/*
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* *
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module mem_array
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* Author: Liwei *
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(
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* *
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input clk,
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* This file is part of the "mips789" project. *
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input [31:0] pc_i,
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* Downloaded from: *
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output [31:0] ins_o,
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* http://www.opencores.org/pdownloads.cgi/list/mips789 *
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input [3:0] wren,
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* *
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input [31:0]din,
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* If you encountered any problem, please contact me via *
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input [31:0]wr_addr_i,
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* Email:mcupro@opencores.org or mcupro@163.com *
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input [31:0]rd_addr_i,
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* *
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output [31:0]dout
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******************************************************************/
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);
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wire [29:0] rd_addr,pc,wr_addr;
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wire [31:0]dout_w;
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module mem_array
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assign dout = dout_w;
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(
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assign rd_addr=rd_addr_i[31:2];
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input clk,
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assign wr_addr=wr_addr_i[31:2];
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input [31:0] pc_i,
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assign pc= pc_i[31:2];
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output [31:0] ins_o,
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input [3:0] wren,
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input [31:0]din,
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input [31:0]data_addr_i,
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`ifdef DEBUG
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output [31:0]dout
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);
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sim_syn_ram3 ram3 (
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wire [31:0] data_addr;
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.data(din[31:31-7]),
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wire [31:0]dout_w;
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.wraddress(wr_addr),
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assign dout = dout_w;
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.rdaddress_a(pc),
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assign data_addr=data_addr_i[31:2];
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.rdaddress_b(rd_addr),
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wire [29:0]pc= pc_i[31:2];
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.wren(wren[3]),
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.clock(clk),
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ram2048x8_3 ram3(
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.qa(ins_o[31:31-7]),
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.data_a(32'b0),
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.qb(dout_w[31:31-7])
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.wren_a(1'b0),
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);
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.address_a(pc),
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.data_b(din[31:24]),
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sim_syn_ram2 ram2(
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.address_b(data_addr),
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.data(din[31-8:31-8-7]),
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.wren_b(wren[3]),
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.wraddress(wr_addr),
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.clock(clk),
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.rdaddress_a(pc),
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.q_a(ins_o[31:24]),
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.rdaddress_b(rd_addr),
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.q_b(dout_w[31:24])
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.wren(wren[2]),
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);
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.clock(clk),
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.qa(ins_o[31-8:31-8-7]),
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ram2048x8_2 ram2(
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.qb(dout_w[31-8:31-7-8])
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.data_a(32'b0),
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);
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.wren_a(1'b0),
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.address_a(pc),
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sim_syn_ram1 ram1(
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.data_b(din[23:16]),
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.data(din[31-16:31-16-7]),
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.address_b(data_addr),
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.wraddress(wr_addr),
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.wren_b(wren[2]),
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.rdaddress_a(pc),
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.clock(clk),
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.rdaddress_b(rd_addr),
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.q_a(ins_o[23:16]),
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.wren(wren[1]),
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.q_b(dout_w[23:16])
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.clock(clk),
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);
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.qa(ins_o[31-16:31-7-16]),
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.qb(dout_w[31-16:31-7-16])
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ram2048x8_1 ram1(
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);
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.data_a(32'b0),
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.wren_a(1'b0),
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sim_syn_ram0 ram0(
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.address_a(pc),
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.data(din[31-24:31-7-24]),
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.data_b(din[15:8]),
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.wraddress(wr_addr),
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.address_b(data_addr),
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.rdaddress_a(pc),
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.wren_b(wren[1]),
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.rdaddress_b(rd_addr),
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.clock(clk),
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.wren(wren[0]),
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.q_a(ins_o[15:8]),
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.clock(clk),
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.q_b(dout_w[15:8])
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.qa(ins_o[31-24:31-7-24]),
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);
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.qb(dout_w[31-24:31-7-24])
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);
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ram2048x8_0 ram0(
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.data_a(32'b0),
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.wren_a(1'b0),
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`else
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.address_a(pc),
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ram4096x8_3 ram3(
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.data_b(din[7:0]),
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.data_a(32'b0),
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.address_b(data_addr),
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.wren_a(1'b0),
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.wren_b(wren[0]),
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.address_a(32'b0),
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.clock(clk),
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.data_b(din[31:24]),
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.q_a(ins_o[7:0]),
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.address_b(wr_addr),
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.q_b(dout_w[7:0])
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.wren_b(wren[3]),
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);
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.clock(clk),
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.q_a(ins_o[31:24]),
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.q_b(dout_w[31:24])
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);
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ram4096x8_2 ram2(
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.data_a(32'b0),
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.wren_a(1'b0),
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.address_a(32'b0),
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.data_b(din[23:16]),
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.address_b(wr_addr),
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.wren_b(wren[2]),
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.clock(clk),
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.q_a(ins_o[23:16]),
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.q_b(dout_w[23:16])
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);
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ram4096x8_1 ram1(
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.data_a(32'b0),
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.wren_a(1'b0),
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.address_a(32'b0),
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.data_b(din[15:8]),
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.address_b(wr_addr),
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.wren_b(wren[1]),
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.clock(clk),
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.q_a(ins_o[15:8]),
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.q_b(dout_w[15:8])
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);
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ram4096x8_0 ram0(
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.data_a(32'b0),
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.wren_a(1'b0),
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.address_a(32'b0),
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.data_b(din[7:0]),
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.address_b(wr_addr),
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.wren_b(wren[0]),
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.clock(clk),
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.q_a(ins_o[7:0]),
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.q_b(dout_w[7:0])
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);
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// `endif
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endmodule
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*/
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endmodule
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No newline at end of file
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