| Line 86... |
Line 86... |
constant C_QLUM_BASE : integer := 44;
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constant C_QLUM_BASE : integer := 44;
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constant C_QCHR_BASE : integer := 44+69;
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constant C_QCHR_BASE : integer := 44+69;
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|
|
|
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signal hr_data : std_logic_vector(7 downto 0);
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signal hr_data : std_logic_vector(7 downto 0);
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signal hr_waddr : std_logic_vector(8 downto 0);
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signal hr_waddr : std_logic_vector(9 downto 0);
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signal hr_raddr : std_logic_vector(8 downto 0);
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signal hr_raddr : std_logic_vector(9 downto 0);
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signal hr_we : std_logic;
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signal hr_we : std_logic;
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signal hr_q : std_logic_vector(7 downto 0);
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signal hr_q : std_logic_vector(7 downto 0);
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signal size_wr_cnt : unsigned(2 downto 0);
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signal size_wr_cnt : unsigned(2 downto 0);
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signal size_wr : std_logic;
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signal size_wr : std_logic;
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signal rd_cnt : unsigned(8 downto 0);
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signal rd_cnt : unsigned(9 downto 0);
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signal rd_en : std_logic;
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signal rd_en : std_logic;
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signal rd_en_d1 : std_logic;
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signal rd_en_d1 : std_logic;
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signal rd_cnt_d1 : unsigned(8 downto 0);
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signal rd_cnt_d1 : unsigned(rd_cnt'range);
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signal rd_cnt_d2 : unsigned(8 downto 0);
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signal rd_cnt_d2 : unsigned(rd_cnt'range);
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signal eoi_cnt : unsigned(1 downto 0);
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signal eoi_cnt : unsigned(1 downto 0);
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signal eoi_wr : std_logic;
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signal eoi_wr : std_logic;
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signal eoi_wr_d1 : std_logic;
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signal eoi_wr_d1 : std_logic;
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|
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-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
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| Line 112... |
Line 112... |
-- Header RAM
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-- Header RAM
|
-------------------------------------------------------------------
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-------------------------------------------------------------------
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U_Header_RAM : entity work.RAMZ
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U_Header_RAM : entity work.RAMZ
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generic map
|
generic map
|
(
|
(
|
RAMADDR_W => 9,
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RAMADDR_W => 10,
|
RAMDATA_W => 8
|
RAMDATA_W => 8
|
)
|
)
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port map
|
port map
|
(
|
(
|
d => hr_data,
|
d => hr_data,
|
