| Line 70... |
Line 70... |
----------------------------------- ARCHITECTURE ------------------------------
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----------------------------------- ARCHITECTURE ------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture RTL of BUF_FIFO is
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architecture RTL of BUF_FIFO is
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constant C_NUM_SUBF : integer := ((C_MAX_LINE_WIDTH/8));
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constant C_NUM_SUBF : integer := C_MAX_LINE_WIDTH/8;
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constant C_PIXEL_BITS : integer := 24;
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constant C_SUBF_ADDRW : integer := 7-C_MEMORY_OPTIMIZED;
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--constant C_LOG2_NUM_SUBF : integer := integer(log2(real(C_NUM_SUBF)));
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type T_DATA_ARR is array (0 to C_NUM_SUBF-1) of std_logic_vector(23 downto 0);
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type T_DATA_ARR is array (0 to C_NUM_SUBF-1) of std_logic_vector(23 downto 0);
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type T_CNT_ARR is array (0 to C_NUM_SUBF-1) of
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type T_CNT_ARR is array (0 to C_NUM_SUBF-1) of
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std_logic_vector(7-C_MEMORY_OPTIMIZED downto 0);
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std_logic_vector(C_SUBF_ADDRW downto 0);
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type T_FIFO_RAMADDR is array (0 to C_NUM_SUBF-1) of
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STD_LOGIC_VECTOR(C_SUBF_ADDRW-1 downto 0);
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signal fifo_rd : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_rd : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_wr : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_wr : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_data : std_logic_vector(23 downto 0);
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signal fifo_data : std_logic_vector(23 downto 0);
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signal fifo_data_d1 : std_logic_vector(23 downto 0);
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signal fifo_data_d1 : std_logic_vector(23 downto 0);
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signal fifo_q : T_DATA_ARR;
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signal fifo_full : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_full : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_empty : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_empty : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_half_full : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_half_full : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_count : T_CNT_ARR;
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signal fifo_count : T_CNT_ARR;
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signal pixel_cnt : unsigned(15 downto 0);
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signal pixel_cnt : unsigned(15 downto 0);
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signal wblock_cnt : unsigned(12 downto 0);
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signal wblock_cnt : unsigned(12 downto 0);
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signal last_idx : unsigned(12 downto 0);
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signal last_idx : unsigned(12 downto 0);
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signal idx_reg : unsigned(log2(C_NUM_SUBF)-1 downto 0);
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signal idx_reg : unsigned(log2(C_NUM_SUBF)-1 downto 0);
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signal wr_idx_reg : unsigned(log2(C_NUM_SUBF)-1 downto 0);
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signal ramq : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
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signal ramd : STD_LOGIC_VECTOR (C_PIXEL_BITS-1 downto 0);
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signal ramwaddr : STD_LOGIC_VECTOR
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(log2(C_NUM_SUBF)+C_SUBF_ADDRW-1 downto 0);
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signal ramwaddr_offset : unsigned(C_SUBF_ADDRW-1 downto 0);
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signal ramwaddr_base : unsigned(log2(C_NUM_SUBF)+C_SUBF_ADDRW downto 0);
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signal ramenw : STD_LOGIC;
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signal ramenw_m1 : STD_LOGIC;
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signal ramenw_m2 : STD_LOGIC;
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signal ramraddr : STD_LOGIC_VECTOR
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(log2(C_NUM_SUBF)+C_SUBF_ADDRW-1 downto 0);
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signal ramraddr_base : unsigned(log2(C_NUM_SUBF)+C_SUBF_ADDRW downto 0);
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signal ramraddr_offset : unsigned(C_SUBF_ADDRW-1 downto 0);
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signal ramenr : STD_LOGIC;
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signal fifo_ramwaddr : T_FIFO_RAMADDR;
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signal fifo_ramenw : STD_LOGIC_VECTOR(C_NUM_SUBF-1 downto 0);
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signal fifo_ramraddr : T_FIFO_RAMADDR;
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signal fifo_ramenr : STD_LOGIC_VECTOR(C_NUM_SUBF-1 downto 0);
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signal offset_ramwaddr : STD_LOGIC_VECTOR(C_SUBF_ADDRW-1 downto 0);
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture: begin
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-- Architecture: begin
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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begin
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begin
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- SUB_FIFOs
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-- SUB_FIFOs
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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G_SUB_FIFO : for i in 0 to C_NUM_SUBF-1 generate
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G_SUB_FIFO : for i in 0 to C_NUM_SUBF-1 generate
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U_SUB_FIFO : entity work.FIFO
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U_SUB_FIFO : entity work.SUB_FIFO
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generic map
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generic map
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(
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(
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DATA_WIDTH => 24,
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DATA_WIDTH => C_PIXEL_BITS,
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ADDR_WIDTH => 7-C_MEMORY_OPTIMIZED
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ADDR_WIDTH => C_SUBF_ADDRW
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)
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)
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port map
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port map
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(
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(
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rst => RST,
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rst => RST,
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clk => CLK,
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clk => CLK,
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rinc => fifo_rd(i),
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rinc => fifo_rd(i),
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winc => fifo_wr(i),
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winc => fifo_wr(i),
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datai => fifo_data,
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datao => fifo_q(i),
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fullo => fifo_full(i),
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fullo => fifo_full(i),
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emptyo => fifo_empty(i),
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emptyo => fifo_empty(i),
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count => fifo_count(i)
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count => fifo_count(i),
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ramwaddr => fifo_ramwaddr(i),
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ramenw => fifo_ramenw(i),
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ramraddr => fifo_ramraddr(i),
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ramenr => fifo_ramenr(i)
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);
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);
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end generate G_SUB_FIFO;
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end generate G_SUB_FIFO;
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- RAM for SUB_FIFOs
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-------------------------------------------------------------------
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U_SUB_RAMZ : entity work.SUB_RAMZ
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generic map
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(
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RAMADDR_W => log2(C_NUM_SUBF)+C_SUBF_ADDRW,
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RAMDATA_W => C_PIXEL_BITS
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)
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port map
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(
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d => ramd,
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waddr => ramwaddr,
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raddr => ramraddr,
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we => ramenw,
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clk => clk,
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q => ramq
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);
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-------------------------------------------------------------------
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-- FIFO almost full
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-- FIFO almost full
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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p_fifo_almost_full : process(CLK, RST)
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p_fifo_almost_full : process(CLK, RST)
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begin
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begin
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if RST = '1' then
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if RST = '1' then
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| Line 199... |
Line 249... |
end if;
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end if;
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end loop;
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end loop;
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end if;
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end if;
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end process;
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end process;
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- Mux1
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-- Mux1
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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p_mux1 : process(CLK, RST)
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p_mux1 : process(CLK, RST)
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begin
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begin
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if RST = '1' then
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if RST = '1' then
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fifo_data <= (others => '0');
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for i in 0 to C_NUM_SUBF-1 loop
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for i in 0 to C_NUM_SUBF-1 loop
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fifo_wr(i) <= '0';
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fifo_wr(i) <= '0';
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end loop;
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end loop;
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elsif CLK'event and CLK = '1' then
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elsif CLK'event and CLK = '1' then
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for i in 0 to C_NUM_SUBF-1 loop
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for i in 0 to C_NUM_SUBF-1 loop
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| Line 218... |
Line 266... |
fifo_wr(i) <= iram_wren;
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fifo_wr(i) <= iram_wren;
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else
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else
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fifo_wr(i) <= '0';
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fifo_wr(i) <= '0';
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end if;
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end if;
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end loop;
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end loop;
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fifo_data <= iram_wdata;
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end if;
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end if;
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end process;
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end process;
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- Mux2
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-- Mux2
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| Line 233... |
Line 279... |
if RST = '1' then
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if RST = '1' then
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for i in 0 to C_NUM_SUBF-1 loop
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for i in 0 to C_NUM_SUBF-1 loop
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fifo_rd(i) <= '0';
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fifo_rd(i) <= '0';
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end loop;
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end loop;
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fdct_fifo_empty <= '0';
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fdct_fifo_empty <= '0';
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fdct_fifo_q <= (others => '0');
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fdct_fifo_hf_full <= '0';
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fdct_fifo_hf_full <= '0';
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idx_reg <= (others => '0');
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idx_reg <= (others => '0');
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elsif CLK'event and CLK = '1' then
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elsif CLK'event and CLK = '1' then
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idx_reg <= unsigned(fdct_block_cnt(log2(C_NUM_SUBF)-1 downto 0));
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idx_reg <= unsigned(fdct_block_cnt(log2(C_NUM_SUBF)-1 downto 0));
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| Line 248... |
Line 293... |
fifo_rd(i) <= '0';
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fifo_rd(i) <= '0';
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end if;
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end if;
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end loop;
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end loop;
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fdct_fifo_empty <= fifo_empty(to_integer(idx_reg));
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fdct_fifo_empty <= fifo_empty(to_integer(idx_reg));
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fdct_fifo_q <= fifo_q(to_integer(idx_reg));
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fdct_fifo_hf_full <= fifo_half_full(to_integer(idx_reg));
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fdct_fifo_hf_full <= fifo_half_full(to_integer(idx_reg));
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end if;
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end if;
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end process;
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end process;
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fdct_fifo_q <= ramq;
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-------------------------------------------------------------------
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-- Mux3
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-------------------------------------------------------------------
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p_mux3 : process(CLK, RST)
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begin
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if RST = '1' then
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ramwaddr <= (others => '0');
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ramwaddr_offset <= (others => '0');
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ramwaddr_base <= (others => '0');
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ramenw <= '0';
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ramenw_m1 <= '0';
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wr_idx_reg <= (others => '0');
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ramd <= (others => '0');
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fifo_data <= (others => '0');
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fifo_data_d1 <= (others => '0');
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elsif CLK'event and CLK = '1' then
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wr_idx_reg <= unsigned(wblock_cnt(log2(C_NUM_SUBF)-1 downto 0));
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fifo_data <= iram_wdata;
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fifo_data_d1 <= fifo_data;
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ramd <= fifo_data_d1;
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ramenw_m1 <= fifo_ramenw(to_integer(wr_idx_reg));
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ramenw <= ramenw_m1;
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ramwaddr_offset <= unsigned(fifo_ramwaddr(to_integer(wr_idx_reg)));
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ramwaddr_base <= to_unsigned(2**C_SUBF_ADDRW, C_SUBF_ADDRW+1) *
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wr_idx_reg;
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ramwaddr <= std_logic_vector(ramwaddr_base(ramwaddr'range) +
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resize(ramwaddr_offset, ramwaddr'length));
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end if;
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end process;
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-------------------------------------------------------------------
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-- Mux4
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-------------------------------------------------------------------
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p_mux4 : process(CLK, RST)
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begin
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if RST = '1' then
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ramraddr <= (others => '0');
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ramraddr_base <= (others => '0');
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ramraddr_offset <= (others => '0');
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elsif CLK'event and CLK = '1' then
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ramraddr_offset <= unsigned(fifo_ramraddr(to_integer(idx_reg)));
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ramraddr_base <= to_unsigned(2**C_SUBF_ADDRW, C_SUBF_ADDRW+1) *
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idx_reg;
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ramraddr <= std_logic_vector(ramraddr_base(ramraddr'range) +
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resize(unsigned(ramraddr_offset), ramraddr'length));
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end if;
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end process;
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end architecture RTL;
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end architecture RTL;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture: end
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-- Architecture: end
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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