| Line 51... |
Line 51... |
img_size_y : in std_logic_vector(15 downto 0);
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img_size_y : in std_logic_vector(15 downto 0);
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sof : in std_logic;
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sof : in std_logic;
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-- HOST DATA
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-- HOST DATA
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iram_wren : in std_logic;
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iram_wren : in std_logic;
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iram_wdata : in std_logic_vector(23 downto 0);
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iram_wdata : in std_logic_vector(C_PIXEL_BITS-1 downto 0);
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fifo_almost_full : out std_logic;
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fifo_almost_full : out std_logic;
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-- FDCT
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-- FDCT
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fdct_block_cnt : in std_logic_vector(12 downto 0);
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fdct_block_cnt : in std_logic_vector(12 downto 0);
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fdct_fifo_rd : in std_logic;
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fdct_fifo_rd : in std_logic;
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| Line 71... |
Line 71... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture RTL of BUF_FIFO is
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architecture RTL of BUF_FIFO is
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constant C_NUM_SUBF : integer := C_MAX_LINE_WIDTH/8;
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constant C_NUM_SUBF : integer := C_MAX_LINE_WIDTH/8;
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constant C_PIXEL_BITS : integer := 24;
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constant C_SUBF_ADDRW : integer := 7-C_MEMORY_OPTIMIZED;
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constant C_SUBF_ADDRW : integer := 7-C_MEMORY_OPTIMIZED;
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--constant C_LOG2_NUM_SUBF : integer := integer(log2(real(C_NUM_SUBF)));
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--constant C_LOG2_NUM_SUBF : integer := integer(log2(real(C_NUM_SUBF)));
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type T_DATA_ARR is array (0 to C_NUM_SUBF-1) of std_logic_vector(23 downto 0);
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type T_DATA_ARR is array (0 to C_NUM_SUBF-1) of std_logic_vector(23 downto 0);
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type T_CNT_ARR is array (0 to C_NUM_SUBF-1) of
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type T_CNT_ARR is array (0 to C_NUM_SUBF-1) of
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| Line 84... |
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type T_FIFO_RAMADDR is array (0 to C_NUM_SUBF-1) of
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type T_FIFO_RAMADDR is array (0 to C_NUM_SUBF-1) of
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STD_LOGIC_VECTOR(C_SUBF_ADDRW-1 downto 0);
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STD_LOGIC_VECTOR(C_SUBF_ADDRW-1 downto 0);
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signal fifo_rd : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_rd : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_wr : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_wr : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_data : std_logic_vector(23 downto 0);
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signal fifo_data : std_logic_vector(C_PIXEL_BITS-1 downto 0);
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signal fifo_data_d1 : std_logic_vector(23 downto 0);
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signal fifo_data_d1 : std_logic_vector(C_PIXEL_BITS-1 downto 0);
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signal fifo_full : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_full : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_empty : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_empty : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_half_full : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_half_full : std_logic_vector(C_NUM_SUBF-1 downto 0);
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signal fifo_count : T_CNT_ARR;
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signal fifo_count : T_CNT_ARR;
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| Line 318... |
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fdct_fifo_empty <= fifo_empty(to_integer(idx_reg));
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fdct_fifo_empty <= fifo_empty(to_integer(idx_reg));
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fdct_fifo_hf_full <= fifo_half_full(to_integer(idx_reg));
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fdct_fifo_hf_full <= fifo_half_full(to_integer(idx_reg));
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end if;
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end if;
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end process;
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end process;
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fdct_fifo_q <= ramq;
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fdct_fifo_q <= (ramq(15 downto 11) & "000" &
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ramq(10 downto 5) & "00" &
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ramq(4 downto 0) & "000") when C_PIXEL_BITS = 16 else ramq;
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- Mux3
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-- Mux3
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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p_mux3 : process(CLK, RST)
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p_mux3 : process(CLK, RST)
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