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[/] [mkjpeg/] [trunk/] [design/] [control/] [CtrlSM.vhd] - Diff between revs 25 and 34

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Rev 25 Rev 34
Line 63... Line 63... 
        -- ZIGZAG
 
        -- ZIGZAG
 
        zig_start          : out std_logic;
 
        zig_start          : out std_logic;
 
        zig_ready          : in  std_logic;
 
        zig_ready          : in  std_logic;
 
        zig_sm_settings    : out T_SM_SETTINGS;
 
        zig_sm_settings    : out T_SM_SETTINGS;
 
 
 
 
 
 
 
        -- Quantizer
 
 
 
        qua_start          : out std_logic;
 
 
 
        qua_ready          : in  std_logic;
 
 
 
        qua_sm_settings    : out T_SM_SETTINGS;
 
 
 
 
 
        -- RLE
 
        -- RLE
 
        rle_start          : out std_logic;
 
        rle_start          : out std_logic;
 
        rle_ready          : in  std_logic;
 
        rle_ready          : in  std_logic;
 
        rle_sm_settings    : out T_SM_SETTINGS;
 
        rle_sm_settings    : out T_SM_SETTINGS;
 
 
 
 
Line 95... Line 100... 
----------------------------------- ARCHITECTURE ------------------------------
 
----------------------------------- ARCHITECTURE ------------------------------
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
architecture RTL of CtrlSM is
 
architecture RTL of CtrlSM is
 
 
 
 
 
 
 
  constant NUM_STAGES   : integer := 6;
 
 
 
 
 
  type T_STATE is (IDLES, JFIF, HORIZ, COMP, VERT, EOI);
 
  type T_STATE is (IDLES, JFIF, HORIZ, COMP, VERT, EOI);
 
  type ARR_FSM is array(5 downto 1) of std_logic_vector(1 downto 0);
 
  type ARR_FSM is array(NUM_STAGES downto 1) of std_logic_vector(1 downto 0);
 
 
 
 
 
  type T_ARR_SM_SETTINGS is array(6 downto 1) of T_SM_SETTINGS;
 
  type T_ARR_SM_SETTINGS is array(NUM_STAGES+1 downto 1) of T_SM_SETTINGS;
 
  signal Reg             : T_ARR_SM_SETTINGS;
 
  signal Reg             : T_ARR_SM_SETTINGS;
 
  signal main_state      : T_STATE;
 
  signal main_state      : T_STATE;
 
  signal start           : std_logic_vector(6 downto 1);
 
  signal start           : std_logic_vector(NUM_STAGES+1 downto 1);
 
  signal idle            : std_logic_vector(6 downto 1);
 
  signal idle            : std_logic_vector(NUM_STAGES+1 downto 1);
 
  signal start_PB        : std_logic_vector(5 downto 1);
 
  signal start_PB        : std_logic_vector(NUM_STAGES downto 1);
 
  signal ready_PB        : std_logic_vector(5 downto 1);
 
  signal ready_PB        : std_logic_vector(NUM_STAGES downto 1);
 
  signal fsm             : ARR_FSM;
 
  signal fsm             : ARR_FSM;
 
  signal start1_d        : std_logic;
 
  signal start1_d        : std_logic;
 
  signal RSM             : T_SM_SETTINGS;
 
  signal RSM             : T_SM_SETTINGS;
 
  signal out_mux_ctrl_s  : std_logic;
 
  signal out_mux_ctrl_s  : std_logic;
 
  signal out_mux_ctrl_s2 : std_logic;
 
  signal out_mux_ctrl_s2 : std_logic;
Line 118... Line 125... 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
begin
 
begin
 
 
 
 
 
  fdct_sm_settings <= Reg(1);
 
  fdct_sm_settings <= Reg(1);
 
  zig_sm_settings  <= Reg(2);
 
  zig_sm_settings  <= Reg(2);
 
  rle_sm_settings  <= Reg(3);
 
  qua_sm_settings  <= Reg(3);
 
  huf_sm_settings  <= Reg(4);
 
  rle_sm_settings  <= Reg(4);
 
  bs_sm_settings   <= Reg(5);
 
  huf_sm_settings  <= Reg(5);
 
 
 
  bs_sm_settings   <= Reg(6);
 
 
 
 
 
  fdct_start    <= start_PB(1);
 
  fdct_start    <= start_PB(1);
 
  ready_PB(1)   <= fdct_ready;
 
  ready_PB(1)   <= fdct_ready;
 
 
 
 
 
  zig_start     <= start_PB(2);
 
  zig_start     <= start_PB(2);
 
  ready_PB(2)   <= zig_ready;
 
  ready_PB(2)   <= zig_ready;
 
 
 
 
 
  rle_start     <= start_PB(3);
 
  qua_start     <= start_PB(3);
 
  ready_PB(3)   <= rle_ready;
 
  ready_PB(3)   <= qua_ready;
 
 
 
 
 
 
 
  rle_start     <= start_PB(4);
 
 
 
  ready_PB(4)   <= rle_ready;
 
 
 
 
 
  huf_start     <= start_PB(4);
 
  huf_start     <= start_PB(5);
 
  ready_PB(4)   <= huf_ready;
 
  ready_PB(5)   <= huf_ready;
 
 
 
 
 
  bs_start      <= start_PB(5);
 
  bs_start      <= start_PB(6);
 
  ready_PB(5)   <= bs_ready;
 
  ready_PB(6)   <= bs_ready;
 
 
 
 
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  -- CTRLSM1..5
 
  -- CTRLSM 1..NUM_STAGES
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  G_S_CTRL_SM : for i in 1 to 5 generate
 
  G_S_CTRL_SM : for i in 1 to NUM_STAGES generate
 
 
 
 
 
    -- CTRLSM1..5
 
    -- CTRLSM 1..NUM_STAGES
 
    U_S_CTRL_SM : entity work.SingleSM
 
    U_S_CTRL_SM : entity work.SingleSM
 
    port map
 
    port map
 
    (
 
    (
 
        CLK          => CLK,
 
        CLK          => CLK,
 
        RST          => RST,
 
        RST          => RST,
Line 162... Line 173... 
        -- state out
 
        -- state out
 
        fsm_o        => fsm(i)
 
        fsm_o        => fsm(i)
 
    );
 
    );
 
  end generate G_S_CTRL_SM;
 
  end generate G_S_CTRL_SM;
 
 
 
 
 
  idle(6) <= '1';
 
  idle(NUM_STAGES+1) <= '1';
 
 
 
 
 
  -------------------------------------------------------------------
 
  -------------------------------------------------------------------
 
  -- Reg1
 
  -- Regs
 
  -------------------------------------------------------------------
 
  -------------------------------------------------------------------
 
  G_REG_SM : for i in 1 to 5 generate
 
  G_REG_SM : for i in 1 to NUM_STAGES generate
 
    p_reg1 : process(CLK, RST)
 
    p_reg1 : process(CLK, RST)
 
    begin
 
    begin
 
      if RST = '1' then
 
      if RST = '1' then
 
        Reg(i) <= C_SM_SETTINGS;
 
        Reg(i) <= C_SM_SETTINGS;
 
      elsif CLK'event and CLK = '1' then
 
      elsif CLK'event and CLK = '1' then
Line 270... Line 281... 
          if RSM.y_cnt < unsigned(img_size_y)-8 then
 
          if RSM.y_cnt < unsigned(img_size_y)-8 then
 
            RSM.x_cnt <= (others => '0');
 
            RSM.x_cnt <= (others => '0');
 
            RSM.y_cnt <= RSM.y_cnt + 8;
 
            RSM.y_cnt <= RSM.y_cnt + 8;
 
            main_state <= HORIZ;
 
            main_state <= HORIZ;
 
          else
 
          else
 
            if idle(1) = '1' and idle(2) = '1' and idle(3) = '1' and
 
            if idle(NUM_STAGES downto 1) = (NUM_STAGES-1 downto 0 => '1') then
 
               idle(4) = '1' and idle(5) = '1' then
 
 
 
              main_state   <= EOI;
 
              main_state   <= EOI;
 
              jfif_eoi     <= '1';
 
              jfif_eoi     <= '1';
 
              out_mux_ctrl_s <= '0';
 
              out_mux_ctrl_s <= '0';
 
              jfif_start   <= '1';
 
              jfif_start   <= '1';
 
            end if;
 
            end if;

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