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[/] [mkjpeg/] [trunk/] [design/] [control/] [CtrlSM.vhd] - Diff between revs 46 and 61

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Rev 46 Rev 61
Line 54... Line 54...
        sof                : in  std_logic;
        sof                : in  std_logic;
        img_size_x         : in  std_logic_vector(15 downto 0);
        img_size_x         : in  std_logic_vector(15 downto 0);
        img_size_y         : in  std_logic_vector(15 downto 0);
        img_size_y         : in  std_logic_vector(15 downto 0);
        jpeg_ready         : out std_logic;
        jpeg_ready         : out std_logic;
        jpeg_busy          : out std_logic;
        jpeg_busy          : out std_logic;
        cmp_max            : in  std_logic_vector(1 downto 0);
 
 
 
        -- FDCT
        -- FDCT
        fdct_start         : out std_logic;
        fdct_start         : out std_logic;
        fdct_ready         : in  std_logic;
        fdct_ready         : in  std_logic;
        fdct_sm_settings   : out T_SM_SETTINGS;
        fdct_sm_settings   : out T_SM_SETTINGS;
Line 106... Line 105...
architecture RTL of CtrlSM is
architecture RTL of CtrlSM is
 
 
 
 
  constant NUM_STAGES   : integer := 6;
  constant NUM_STAGES   : integer := 6;
 
 
 
  constant CMP_MAX      : std_logic_vector(2 downto 0) := "100";
 
 
  type T_STATE is (IDLES, JFIF, HORIZ, COMP, VERT, EOI);
  type T_STATE is (IDLES, JFIF, HORIZ, COMP, VERT, EOI);
  type ARR_FSM is array(NUM_STAGES downto 1) of std_logic_vector(1 downto 0);
  type ARR_FSM is array(NUM_STAGES downto 1) of std_logic_vector(1 downto 0);
 
 
  type T_ARR_SM_SETTINGS is array(NUM_STAGES+1 downto 1) of T_SM_SETTINGS;
  type T_ARR_SM_SETTINGS is array(NUM_STAGES+1 downto 1) of T_SM_SETTINGS;
  signal Reg             : T_ARR_SM_SETTINGS;
  signal Reg             : T_ARR_SM_SETTINGS;
Line 267... Line 268...
        -------------------------------
        -------------------------------
        -- COMP
        -- COMP
        -------------------------------
        -------------------------------
        when COMP =>
        when COMP =>
          if idle(1) = '1' and start(1) = '0' then
          if idle(1) = '1' and start(1) = '0' then
            if RSM.cmp_idx < unsigned(cmp_max) then
            if RSM.cmp_idx < unsigned(CMP_MAX) then
              start(1)   <= '1';
              start(1)   <= '1';
            else
            else
              RSM.cmp_idx    <= (others => '0');
              RSM.cmp_idx    <= (others => '0');
              RSM.x_cnt      <= RSM.x_cnt + 8;
              RSM.x_cnt      <= RSM.x_cnt + 16;
              main_state <= HORIZ;
              main_state <= HORIZ;
            end if;
            end if;
          end if;
          end if;
 
 
        -------------------------------
        -------------------------------

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