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[/] [mkjpeg/] [trunk/] [design/] [mdct/] [DCT1D.vhd] - Diff between revs 67 and 71

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Rev 67 Rev 71
Line 77... Line 77... 
  signal even_not_odd_d3 : std_logic;
 
  signal even_not_odd_d3 : std_logic;
 
  signal ramwe_d1        : STD_LOGIC;
 
  signal ramwe_d1        : STD_LOGIC;
 
  signal ramwe_d2        : STD_LOGIC;
 
  signal ramwe_d2        : STD_LOGIC;
 
  signal ramwe_d3        : STD_LOGIC;
 
  signal ramwe_d3        : STD_LOGIC;
 
  signal ramwe_d4        : STD_LOGIC;
 
  signal ramwe_d4        : STD_LOGIC;
 
 
 
  signal ramwe_d5        : STD_LOGIC;
 
 
 
  signal ramwe_d6        : STD_LOGIC;
 
  signal ramwaddro_d1    : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
 
  signal ramwaddro_d1    : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
 
  signal ramwaddro_d2    : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
 
  signal ramwaddro_d2    : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
 
  signal ramwaddro_d3    : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
 
  signal ramwaddro_d3    : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
 
  signal ramwaddro_d4    : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
 
  signal ramwaddro_d4    : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
 
  signal ramwaddro_d5    : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
 
  signal ramwaddro_d5    : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
Line 89... Line 91... 
  signal wmemsel_d2      : STD_LOGIC;
 
  signal wmemsel_d2      : STD_LOGIC;
 
  signal wmemsel_d3      : STD_LOGIC;
 
  signal wmemsel_d3      : STD_LOGIC;
 
  signal wmemsel_d4      : STD_LOGIC;
 
  signal wmemsel_d4      : STD_LOGIC;
 
  signal wmemsel_d5      : STD_LOGIC;
 
  signal wmemsel_d5      : STD_LOGIC;
 
  signal wmemsel_d6      : STD_LOGIC;
 
  signal wmemsel_d6      : STD_LOGIC;
 
 
 
  signal wmemsel_d7      : STD_LOGIC;
 
  signal romedatao_d1    : T_ROM1DATAO;
 
  signal romedatao_d1    : T_ROM1DATAO;
 
  signal romodatao_d1    : T_ROM1DATAO;
 
  signal romodatao_d1    : T_ROM1DATAO;
 
  signal romedatao_d2    : T_ROM1DATAO;
 
  signal romedatao_d2    : T_ROM1DATAO;
 
  signal romodatao_d2    : T_ROM1DATAO;
 
  signal romodatao_d2    : T_ROM1DATAO;
 
  signal romedatao_d3    : T_ROM1DATAO;
 
  signal romedatao_d3    : T_ROM1DATAO;
Line 124... Line 127... 
end component;
 
end component;
 
 
 
 
 
begin
 
begin
 
 
 
 
 
  ramwaddro <= ramwaddro_d6;
 
  ramwaddro <= ramwaddro_d6;
 
  --ramwe     <= ramwe_d4;
 
  wmemsel   <= wmemsel_d6; --wmemsel_d4;
 
  --ramdatai  <= dcto_4(DA_W-1 downto 12);
 
 
 
  wmemsel   <= wmemsel_d4;
 
 
 
 
 
 
 
  odv <= ramwe_d4;
 
  odv <= ramwe_d6;
 
  dcto <= STD_LOGIC_VECTOR(RESIZE(SIGNED(fpr_out),12));
 
  dcto <= STD_LOGIC_VECTOR(RESIZE(SIGNED(fpr_out),12));
 
 
 
 
 
  ramdatai <= fpr_out;
 
  ramdatai <= fpr_out;
 
 
 
 
 
  U_FinitePrecRndNrst : FinitePrecRndNrst
 
  U_FinitePrecRndNrst : FinitePrecRndNrst
Line 245... Line 246... 
      even_not_odd_d3 <= '0';
 
      even_not_odd_d3 <= '0';
 
      ramwe_d1        <= '0';
 
      ramwe_d1        <= '0';
 
      ramwe_d2        <= '0';
 
      ramwe_d2        <= '0';
 
      ramwe_d3        <= '0';
 
      ramwe_d3        <= '0';
 
      ramwe_d4        <= '0';
 
      ramwe_d4        <= '0';
 
 
 
      ramwe_d5        <= '0';
 
 
 
      ramwe_d6        <= '0';
 
      ramwaddro_d1    <= (others => '0');
 
      ramwaddro_d1    <= (others => '0');
 
      ramwaddro_d2    <= (others => '0');
 
      ramwaddro_d2    <= (others => '0');
 
      ramwaddro_d3    <= (others => '0');
 
      ramwaddro_d3    <= (others => '0');
 
      ramwaddro_d4    <= (others => '0');
 
      ramwaddro_d4    <= (others => '0');
 
 
 
      ramwaddro_d5    <= (others => '0');
 
 
 
      ramwaddro_d6    <= (others => '0');
 
      wmemsel_d1      <= '0';
 
      wmemsel_d1      <= '0';
 
      wmemsel_d2      <= '0';
 
      wmemsel_d2      <= '0';
 
      wmemsel_d3      <= '0';
 
      wmemsel_d3      <= '0';
 
      wmemsel_d4      <= '0';
 
      wmemsel_d4      <= '0';
 
 
 
      wmemsel_d5      <= '0';
 
 
 
      wmemsel_d6      <= '0';
 
 
 
      wmemsel_d7      <= '0';
 
      dcto_1          <= (others => '0');
 
      dcto_1          <= (others => '0');
 
      dcto_2          <= (others => '0');
 
      dcto_2          <= (others => '0');
 
      dcto_3          <= (others => '0');
 
      dcto_3          <= (others => '0');
 
      dcto_4          <= (others => '0');
 
      dcto_4          <= (others => '0');
 
    elsif CLK'event and CLK = '1' then
 
    elsif CLK'event and CLK = '1' then
Line 266... Line 274... 
      even_not_odd_d3 <= even_not_odd_d2;
 
      even_not_odd_d3 <= even_not_odd_d2;
 
      ramwe_d1        <= ramwe_s;
 
      ramwe_d1        <= ramwe_s;
 
      ramwe_d2        <= ramwe_d1;
 
      ramwe_d2        <= ramwe_d1;
 
      ramwe_d3        <= ramwe_d2;
 
      ramwe_d3        <= ramwe_d2;
 
      ramwe_d4        <= ramwe_d3;
 
      ramwe_d4        <= ramwe_d3;
 
 
 
      ramwe_d5        <= ramwe_d4;
 
 
 
      ramwe_d6        <= ramwe_d5;
 
      ramwaddro_d1    <= ramwaddro_s;
 
      ramwaddro_d1    <= ramwaddro_s;
 
      ramwaddro_d2    <= ramwaddro_d1;
 
      ramwaddro_d2    <= ramwaddro_d1;
 
      ramwaddro_d3    <= ramwaddro_d2;
 
      ramwaddro_d3    <= ramwaddro_d2;
 
      ramwaddro_d4    <= ramwaddro_d3;
 
      ramwaddro_d4    <= ramwaddro_d3;
 
      ramwaddro_d5    <= ramwaddro_d4;
 
      ramwaddro_d5    <= ramwaddro_d4;
Line 278... Line 288... 
      wmemsel_d2      <= wmemsel_d1;
 
      wmemsel_d2      <= wmemsel_d1;
 
      wmemsel_d3      <= wmemsel_d2;
 
      wmemsel_d3      <= wmemsel_d2;
 
      wmemsel_d4      <= wmemsel_d3;
 
      wmemsel_d4      <= wmemsel_d3;
 
      wmemsel_d5      <= wmemsel_d4;
 
      wmemsel_d5      <= wmemsel_d4;
 
      wmemsel_d6      <= wmemsel_d5;
 
      wmemsel_d6      <= wmemsel_d5;
 
 
 
      wmemsel_d7      <= wmemsel_d6;
 
 
 
 
 
      if even_not_odd = '0' then
 
      if even_not_odd = '0' then
 
        dcto_1 <= STD_LOGIC_VECTOR(RESIZE
 
        dcto_1 <= STD_LOGIC_VECTOR(RESIZE
 
          (RESIZE(SIGNED(romedatao(0)),DA_W) +
 
          (RESIZE(SIGNED(romedatao(0)),DA_W) +
 
          (RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
 
          (RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +

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