Line 77... |
Line 77... |
signal even_not_odd_d3 : std_logic;
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signal even_not_odd_d3 : std_logic;
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signal ramwe_d1 : STD_LOGIC;
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signal ramwe_d1 : STD_LOGIC;
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signal ramwe_d2 : STD_LOGIC;
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signal ramwe_d2 : STD_LOGIC;
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signal ramwe_d3 : STD_LOGIC;
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signal ramwe_d3 : STD_LOGIC;
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signal ramwe_d4 : STD_LOGIC;
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signal ramwe_d4 : STD_LOGIC;
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signal ramwe_d5 : STD_LOGIC;
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signal ramwe_d6 : STD_LOGIC;
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signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal ramwaddro_d5 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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signal ramwaddro_d5 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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Line 89... |
Line 91... |
signal wmemsel_d2 : STD_LOGIC;
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signal wmemsel_d2 : STD_LOGIC;
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signal wmemsel_d3 : STD_LOGIC;
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signal wmemsel_d3 : STD_LOGIC;
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signal wmemsel_d4 : STD_LOGIC;
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signal wmemsel_d4 : STD_LOGIC;
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signal wmemsel_d5 : STD_LOGIC;
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signal wmemsel_d5 : STD_LOGIC;
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signal wmemsel_d6 : STD_LOGIC;
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signal wmemsel_d6 : STD_LOGIC;
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signal wmemsel_d7 : STD_LOGIC;
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signal romedatao_d1 : T_ROM1DATAO;
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signal romedatao_d1 : T_ROM1DATAO;
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signal romodatao_d1 : T_ROM1DATAO;
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signal romodatao_d1 : T_ROM1DATAO;
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signal romedatao_d2 : T_ROM1DATAO;
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signal romedatao_d2 : T_ROM1DATAO;
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signal romodatao_d2 : T_ROM1DATAO;
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signal romodatao_d2 : T_ROM1DATAO;
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signal romedatao_d3 : T_ROM1DATAO;
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signal romedatao_d3 : T_ROM1DATAO;
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Line 127... |
end component;
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end component;
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begin
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begin
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ramwaddro <= ramwaddro_d6;
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ramwaddro <= ramwaddro_d6;
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--ramwe <= ramwe_d4;
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wmemsel <= wmemsel_d6; --wmemsel_d4;
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--ramdatai <= dcto_4(DA_W-1 downto 12);
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wmemsel <= wmemsel_d4;
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odv <= ramwe_d4;
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odv <= ramwe_d6;
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dcto <= STD_LOGIC_VECTOR(RESIZE(SIGNED(fpr_out),12));
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dcto <= STD_LOGIC_VECTOR(RESIZE(SIGNED(fpr_out),12));
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ramdatai <= fpr_out;
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ramdatai <= fpr_out;
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U_FinitePrecRndNrst : FinitePrecRndNrst
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U_FinitePrecRndNrst : FinitePrecRndNrst
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Line 245... |
Line 246... |
even_not_odd_d3 <= '0';
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even_not_odd_d3 <= '0';
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ramwe_d1 <= '0';
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ramwe_d1 <= '0';
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ramwe_d2 <= '0';
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ramwe_d2 <= '0';
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ramwe_d3 <= '0';
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ramwe_d3 <= '0';
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ramwe_d4 <= '0';
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ramwe_d4 <= '0';
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ramwe_d5 <= '0';
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ramwe_d6 <= '0';
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ramwaddro_d1 <= (others => '0');
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ramwaddro_d1 <= (others => '0');
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ramwaddro_d2 <= (others => '0');
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ramwaddro_d2 <= (others => '0');
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ramwaddro_d3 <= (others => '0');
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ramwaddro_d3 <= (others => '0');
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ramwaddro_d4 <= (others => '0');
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ramwaddro_d4 <= (others => '0');
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ramwaddro_d5 <= (others => '0');
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ramwaddro_d6 <= (others => '0');
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wmemsel_d1 <= '0';
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wmemsel_d1 <= '0';
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wmemsel_d2 <= '0';
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wmemsel_d2 <= '0';
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wmemsel_d3 <= '0';
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wmemsel_d3 <= '0';
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wmemsel_d4 <= '0';
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wmemsel_d4 <= '0';
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wmemsel_d5 <= '0';
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wmemsel_d6 <= '0';
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wmemsel_d7 <= '0';
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dcto_1 <= (others => '0');
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dcto_1 <= (others => '0');
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dcto_2 <= (others => '0');
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dcto_2 <= (others => '0');
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dcto_3 <= (others => '0');
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dcto_3 <= (others => '0');
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dcto_4 <= (others => '0');
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dcto_4 <= (others => '0');
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elsif CLK'event and CLK = '1' then
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elsif CLK'event and CLK = '1' then
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Line 266... |
Line 274... |
even_not_odd_d3 <= even_not_odd_d2;
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even_not_odd_d3 <= even_not_odd_d2;
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ramwe_d1 <= ramwe_s;
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ramwe_d1 <= ramwe_s;
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ramwe_d2 <= ramwe_d1;
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ramwe_d2 <= ramwe_d1;
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ramwe_d3 <= ramwe_d2;
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ramwe_d3 <= ramwe_d2;
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ramwe_d4 <= ramwe_d3;
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ramwe_d4 <= ramwe_d3;
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ramwe_d5 <= ramwe_d4;
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ramwe_d6 <= ramwe_d5;
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ramwaddro_d1 <= ramwaddro_s;
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ramwaddro_d1 <= ramwaddro_s;
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ramwaddro_d2 <= ramwaddro_d1;
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ramwaddro_d2 <= ramwaddro_d1;
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ramwaddro_d3 <= ramwaddro_d2;
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ramwaddro_d3 <= ramwaddro_d2;
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ramwaddro_d4 <= ramwaddro_d3;
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ramwaddro_d4 <= ramwaddro_d3;
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ramwaddro_d5 <= ramwaddro_d4;
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ramwaddro_d5 <= ramwaddro_d4;
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Line 288... |
wmemsel_d2 <= wmemsel_d1;
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wmemsel_d2 <= wmemsel_d1;
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wmemsel_d3 <= wmemsel_d2;
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wmemsel_d3 <= wmemsel_d2;
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wmemsel_d4 <= wmemsel_d3;
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wmemsel_d4 <= wmemsel_d3;
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wmemsel_d5 <= wmemsel_d4;
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wmemsel_d5 <= wmemsel_d4;
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wmemsel_d6 <= wmemsel_d5;
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wmemsel_d6 <= wmemsel_d5;
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wmemsel_d7 <= wmemsel_d6;
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if even_not_odd = '0' then
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if even_not_odd = '0' then
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dcto_1 <= STD_LOGIC_VECTOR(RESIZE
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dcto_1 <= STD_LOGIC_VECTOR(RESIZE
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(RESIZE(SIGNED(romedatao(0)),DA_W) +
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(RESIZE(SIGNED(romedatao(0)),DA_W) +
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(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
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(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
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