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[/] [mkjpeg/] [trunk/] [design/] [mdct/] [DCT2D.VHD] - Diff between revs 25 and 67
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| Rev 25 |
Rev 67 |
| Line 87... |
Line 87... |
signal romodatao_d2 : T_ROM2DATAO;
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signal romodatao_d2 : T_ROM2DATAO;
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signal romedatao_d3 : T_ROM2DATAO;
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signal romedatao_d3 : T_ROM2DATAO;
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signal romodatao_d3 : T_ROM2DATAO;
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signal romodatao_d3 : T_ROM2DATAO;
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signal romedatao_d4 : T_ROM2DATAO;
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signal romedatao_d4 : T_ROM2DATAO;
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signal romodatao_d4 : T_ROM2DATAO;
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signal romodatao_d4 : T_ROM2DATAO;
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signal odv_s : std_logic;
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signal dcto_s : std_logic_vector(OP_W-1 downto 0);
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component FinitePrecRndNrst is
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generic
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(
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C_IN_SZ : natural := 37;
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C_OUT_SZ : natural := 16;
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C_FRAC_SZ : natural := 15
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);
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port (
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CLK : in std_logic;
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RST : in std_logic;
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datain : in STD_LOGIC_VECTOR(C_IN_SZ-1 downto 0);
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dataval : in std_logic;
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dataout : out STD_LOGIC_VECTOR(C_OUT_SZ-1 downto 0);
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clip_inc : out std_logic;
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dval_out : out std_logic
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);
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end component;
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begin
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begin
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ramraddro_sg:
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ramraddro_sg:
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ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
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ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
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| Line 301... |
Line 324... |
DA2_W));
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DA2_W));
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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dcto <= dcto_5(DA2_W-1 downto 12);
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dcto <= dcto_s;
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odv <= odv_d5;
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odv <= odv_s;
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U_FinitePrecRndNrst : FinitePrecRndNrst
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generic map(
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C_IN_SZ => DA2_W,
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C_OUT_SZ => DA2_W-12,
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C_FRAC_SZ => 12
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)
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port map(
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CLK => clk,
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RST => rst,
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datain => dcto_5,
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dataval => odv_d5,
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dataout => dcto_s,
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clip_inc => open,
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dval_out => odv_s
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);
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p_romaddr : process(CLK, RST)
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p_romaddr : process(CLK, RST)
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begin
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begin
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if RST = '1' then
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if RST = '1' then
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romeaddro <= (others => (others => '0'));
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romeaddro <= (others => (others => '0'));
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