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[/] [mkjpeg/] [trunk/] [design/] [mdct/] [FDCT.vhd] - Diff between revs 28 and 52

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Rev 28 Rev 52
Line 50... Line 50...
        start_pb           : in  std_logic;
        start_pb           : in  std_logic;
        ready_pb           : out std_logic;
        ready_pb           : out std_logic;
        fdct_sm_settings   : in  T_SM_SETTINGS;
        fdct_sm_settings   : in  T_SM_SETTINGS;
 
 
        -- BUF_FIFO
        -- BUF_FIFO
        bf_block_cnt       : out std_logic_vector(12 downto 0);
 
        bf_fifo_rd         : out std_logic;
        bf_fifo_rd         : out std_logic;
        bf_fifo_empty      : in  std_logic;
 
        bf_fifo_q          : in  std_logic_vector(23 downto 0);
        bf_fifo_q          : in  std_logic_vector(23 downto 0);
        bf_fifo_hf_full    : in  std_logic;
        bf_fifo_hf_full    : in  std_logic;
 
 
        -- ZIG ZAG
        -- ZIG ZAG
        zz_buf_sel         : in  std_logic;
        zz_buf_sel         : in  std_logic;
Line 93... Line 91...
  signal mdct_idval        : std_logic;
  signal mdct_idval        : std_logic;
  signal mdct_odval        : std_logic;
  signal mdct_odval        : std_logic;
  signal mdct_data_out     : std_logic_vector(11 downto 0);
  signal mdct_data_out     : std_logic_vector(11 downto 0);
  signal odv1              : std_logic;
  signal odv1              : std_logic;
  signal dcto1             : std_logic_vector(11 downto 0);
  signal dcto1             : std_logic_vector(11 downto 0);
  signal x_block_cnt       : unsigned(15 downto 0);
  signal x_pixel_cnt       : unsigned(15 downto 0);
  signal y_block_cnt       : unsigned(15 downto 0);
  signal y_line_cnt        : unsigned(15 downto 0);
  signal x_block_cnt_cur   : unsigned(15 downto 0);
 
  signal y_block_cnt_cur   : unsigned(15 downto 0);
 
  signal rd_addr           : std_logic_vector(31 downto 0);
  signal rd_addr           : std_logic_vector(31 downto 0);
  signal input_rd_cnt      : unsigned(5 downto 0);
  signal input_rd_cnt      : unsigned(5 downto 0);
  signal rd_en             : std_logic;
  signal rd_en             : std_logic;
  signal rd_en_d1          : std_logic;
  signal rd_en_d1          : std_logic;
  signal rdaddr            : unsigned(31 downto 0);
  signal rdaddr            : unsigned(31 downto 0);
  signal bf_dval           : std_logic_vector(3 downto 0);
  signal bf_dval           : std_logic;
 
  signal bf_dval_m1        : std_logic;
 
  signal bf_dval_m2        : std_logic;
  signal wr_cnt            : unsigned(5 downto 0);
  signal wr_cnt            : unsigned(5 downto 0);
  signal dbuf_data         : std_logic_vector(11 downto 0);
  signal dbuf_data         : std_logic_vector(11 downto 0);
  signal dbuf_q            : std_logic_vector(11 downto 0);
  signal dbuf_q            : std_logic_vector(11 downto 0);
  signal dbuf_we           : std_logic;
  signal dbuf_we           : std_logic;
  signal dbuf_waddr        : std_logic_vector(6 downto 0);
  signal dbuf_waddr        : std_logic_vector(6 downto 0);
Line 166... Line 164...
  signal fram1_we          : std_logic;
  signal fram1_we          : std_logic;
  signal fram1_waddr       : std_logic_vector(5 downto 0);
  signal fram1_waddr       : std_logic_vector(5 downto 0);
  signal fram1_raddr       : std_logic_vector(5 downto 0);
  signal fram1_raddr       : std_logic_vector(5 downto 0);
  signal fram1_rd_d        : std_logic_vector(8 downto 0);
  signal fram1_rd_d        : std_logic_vector(8 downto 0);
  signal fram1_rd          : std_logic;
  signal fram1_rd          : std_logic;
  signal bf_fifo_empty_d1  : std_logic;
 
  signal rd_started        : std_logic;
  signal rd_started        : std_logic;
  signal writing_en        : std_logic;
  signal writing_en        : std_logic;
 
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Architecture: begin
-- Architecture: begin
Line 178... Line 175...
begin
begin
 
 
  zz_data      <= dbuf_q;
  zz_data      <= dbuf_q;
 
 
  bf_fifo_rd   <= bf_fifo_rd_s;
  bf_fifo_rd   <= bf_fifo_rd_s;
  bf_block_cnt <= std_logic_vector(x_block_cnt_cur(15 downto 3));
 
 
 
  -------------------------------------------------------------------
  -------------------------------------------------------------------
  -- FRAM1
  -- FRAM1
  -------------------------------------------------------------------
  -------------------------------------------------------------------
  U_FRAM1 : entity work.RAMZ
  U_FRAM1 : entity work.RAMZ
Line 200... Line 196...
        clk         => CLK,
        clk         => CLK,
 
 
        q           => fram1_q
        q           => fram1_q
  );
  );
 
 
  fram1_we   <= bf_dval(bf_dval'high);
  fram1_we   <= bf_dval;
  fram1_data <= bf_fifo_q;
  fram1_data <= bf_fifo_q;
 
 
  -------------------------------------------------------------------
  -------------------------------------------------------------------
  -- FRAM1 process
  -- FRAM1 process
  -------------------------------------------------------------------
  -------------------------------------------------------------------
Line 225... Line 221...
  p_counter1 : process(CLK, RST)
  p_counter1 : process(CLK, RST)
  begin
  begin
    if RST = '1' then
    if RST = '1' then
      rd_en           <= '0';
      rd_en           <= '0';
      rd_en_d1        <= '0';
      rd_en_d1        <= '0';
      x_block_cnt     <= (others => '0');
      x_pixel_cnt     <= (others => '0');
      y_block_cnt     <= (others => '0');
      y_line_cnt     <= (others => '0');
      input_rd_cnt    <= (others => '0');
      input_rd_cnt    <= (others => '0');
      cmp_idx         <= (others => '0');
      cmp_idx         <= (others => '0');
      cur_cmp_idx     <= (others => '0');
      cur_cmp_idx     <= (others => '0');
      cur_cmp_idx_d1  <= (others => '0');
      cur_cmp_idx_d1  <= (others => '0');
      cur_cmp_idx_d2  <= (others => '0');
      cur_cmp_idx_d2  <= (others => '0');
Line 240... Line 236...
      cur_cmp_idx_d6  <= (others => '0');
      cur_cmp_idx_d6  <= (others => '0');
      cur_cmp_idx_d7  <= (others => '0');
      cur_cmp_idx_d7  <= (others => '0');
      cur_cmp_idx_d8  <= (others => '0');
      cur_cmp_idx_d8  <= (others => '0');
      cur_cmp_idx_d9  <= (others => '0');
      cur_cmp_idx_d9  <= (others => '0');
      eoi_fdct        <= '0';
      eoi_fdct        <= '0';
      x_block_cnt_cur <= (others => '0');
 
      y_block_cnt_cur <= (others => '0');
 
      start_int       <= '0';
      start_int       <= '0';
      bf_fifo_rd_s    <= '0';
      bf_fifo_rd_s    <= '0';
      bf_dval         <= (others => '0');
      bf_dval         <= '0';
 
      bf_dval_m1      <= '0';
 
      bf_dval_m2      <= '0';
      fram1_rd        <= '0';
      fram1_rd        <= '0';
      fram1_rd_d      <= (others => '0');
      fram1_rd_d      <= (others => '0');
      fram1_raddr     <= (others => '0');
      fram1_raddr     <= (others => '0');
    elsif CLK'event and CLK = '1' then
    elsif CLK'event and CLK = '1' then
      rd_en_d1 <= rd_en;
      rd_en_d1 <= rd_en;
Line 261... Line 257...
      cur_cmp_idx_d7 <= cur_cmp_idx_d6;
      cur_cmp_idx_d7 <= cur_cmp_idx_d6;
      cur_cmp_idx_d8 <= cur_cmp_idx_d7;
      cur_cmp_idx_d8 <= cur_cmp_idx_d7;
      cur_cmp_idx_d9 <= cur_cmp_idx_d8;
      cur_cmp_idx_d9 <= cur_cmp_idx_d8;
      start_int      <= '0';
      start_int      <= '0';
 
 
      bf_dval        <= bf_dval(bf_dval'length-2 downto 0) & bf_fifo_rd_s;
      bf_dval_m2     <= bf_fifo_rd_s;
 
      bf_dval_m1     <= bf_dval_m2;
 
      bf_dval        <= bf_dval_m1;
      fram1_rd_d     <= fram1_rd_d(fram1_rd_d'length-2 downto 0) & fram1_rd;
      fram1_rd_d     <= fram1_rd_d(fram1_rd_d'length-2 downto 0) & fram1_rd;
 
 
      -- SOF or internal self-start
      -- SOF or internal self-start
      if (sof = '1' or start_int = '1') then
      if (sof = '1' or start_int = '1') then
        input_rd_cnt <= (others => '0');
        input_rd_cnt <= (others => '0');
Line 274... Line 272...
 
 
        -- component index
        -- component index
        if cmp_idx = 3-1 then
        if cmp_idx = 3-1 then
          cmp_idx <= (others => '0');
          cmp_idx <= (others => '0');
          -- horizontal block counter
          -- horizontal block counter
          if x_block_cnt = unsigned(img_size_x)-8 then
          if x_pixel_cnt = unsigned(img_size_x)-8 then
            x_block_cnt <= (others => '0');
            x_pixel_cnt <= (others => '0');
            -- vertical block counter
            -- vertical block counter
            if y_block_cnt = unsigned(img_size_y)-8 then
            if y_line_cnt = unsigned(img_size_y)-8 then
              y_block_cnt <= (others => '0');
              y_line_cnt <= (others => '0');
 
              -- set end of image flag
              eoi_fdct <= '1';
              eoi_fdct <= '1';
            else
            else
              y_block_cnt <= y_block_cnt + 8;
              y_line_cnt <= y_line_cnt + 8;
            end if;
            end if;
          else
          else
            x_block_cnt <= x_block_cnt + 8;
            x_pixel_cnt <= x_pixel_cnt + 8;
          end if;
          end if;
        else
        else
          cmp_idx <=cmp_idx + 1;
          cmp_idx <=cmp_idx + 1;
        end if;
        end if;
 
 
        x_block_cnt_cur <= x_block_cnt;
 
        y_block_cnt_cur <= y_block_cnt;
 
        cur_cmp_idx     <= cmp_idx;
        cur_cmp_idx     <= cmp_idx;
      end if;
      end if;
 
 
      -- wait until FIFO becomes half full
      -- wait until FIFO becomes half full but only for component 0
 
      -- as we read buf FIFO only during component 0
      if rd_started = '1' and (bf_fifo_hf_full = '1' or cur_cmp_idx /= 0) then
      if rd_started = '1' and (bf_fifo_hf_full = '1' or cur_cmp_idx /= 0) then
        rd_en      <= '1';
        rd_en      <= '1';
        rd_started <= '0';
        rd_started <= '0';
      end if;
      end if;
 
 
Line 314... Line 312...
        end if;
        end if;
 
 
        -- count number of samples read from input in one run
        -- count number of samples read from input in one run
        if input_rd_cnt = 64-1 then
        if input_rd_cnt = 64-1 then
          rd_en        <= '0';
          rd_en        <= '0';
 
          -- internal restart
          start_int    <= '1' and not eoi_fdct;
          start_int    <= '1' and not eoi_fdct;
          eoi_fdct     <= '0';
          eoi_fdct     <= '0';
        else
        else
          input_rd_cnt <= input_rd_cnt + 1;
          input_rd_cnt <= input_rd_cnt + 1;
        end if;
        end if;
Line 404... Line 403...
  fifo_data_in <= mdct_data_out;
  fifo_data_in <= mdct_data_out;
 
 
 
 
 
 
  -------------------------------------------------------------------
  -------------------------------------------------------------------
  -- FIFO rd controller
  -- FIFO1 rd controller
  -------------------------------------------------------------------
  -------------------------------------------------------------------
  p_fifo_rd_ctrl : process(CLK, RST)
  p_fifo_rd_ctrl : process(CLK, RST)
  begin
  begin
    if RST = '1' then
    if RST = '1' then
      fifo1_rd     <= '0';
      fifo1_rd     <= '0';

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