| Line 74... |
Line 74... |
signal rd_cnt : unsigned(5 downto 0);
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signal rd_cnt : unsigned(5 downto 0);
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signal rd_en : std_logic;
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signal rd_en : std_logic;
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signal divalid : STD_LOGIC;
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signal divalid : STD_LOGIC;
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signal zrl_proc : std_logic;
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signal zrl_proc : std_logic;
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signal zrl_proc_d1 : std_logic;
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signal zrl_di : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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signal zrl_di : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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begin
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begin
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size <= STD_LOGIC_VECTOR(size_reg);
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size <= STD_LOGIC_VECTOR(size_reg);
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amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));
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amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));
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rd_addr <= STD_LOGIC_VECTOR(rd_cnt);
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rd_addr <= STD_LOGIC_VECTOR(rd_cnt);
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-------------------------------------------
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-------------------------------------------
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-- Counter1
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-------------------------------------------
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process(clk,rst)
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begin
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if rst = '1' then
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rd_en <= '0';
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rd_cnt <= (others => '0');
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elsif clk = '1' and clk'event then
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if start_pb = '1' then
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rd_cnt <= (others => '0');
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rd_en <= '1';
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end if;
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-- input read enable
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if rd_en = '1' and zrl_proc = '0' then
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if rd_cnt = 64-1 then
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rd_cnt <= (others => '0');
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rd_en <= '0';
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else
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rd_cnt <= rd_cnt + 1;
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end if;
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end if;
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end if;
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end process;
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-------------------------------------------
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-- MAIN PROCESSING
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-- MAIN PROCESSING
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-------------------------------------------
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-------------------------------------------
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process(clk,rst)
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process(clk,rst)
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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| Line 126... |
Line 99... |
runlength_reg <= (others => '0');
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runlength_reg <= (others => '0');
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runlength <= (others => '0');
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runlength <= (others => '0');
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dovalid <= '0';
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dovalid <= '0';
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zero_cnt <= (others => '0');
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zero_cnt <= (others => '0');
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zrl_proc <= '0';
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zrl_proc <= '0';
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zrl_proc_d1 <= '0';
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rd_en <= '0';
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rd_cnt <= (others => '0');
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elsif clk = '1' and clk'event then
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elsif clk = '1' and clk'event then
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dovalid_reg <= '0';
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dovalid_reg <= '0';
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runlength_reg <= (others => '0');
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runlength_reg <= (others => '0');
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wr_cnt_d1 <= wr_cnt;
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wr_cnt_d1 <= wr_cnt;
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runlength <= std_logic_vector(runlength_reg);
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runlength <= std_logic_vector(runlength_reg);
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dovalid <= dovalid_reg;
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dovalid <= dovalid_reg;
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divalid <= rd_en;
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divalid <= rd_en;
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zrl_proc_d1 <= zrl_proc;
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if start_pb = '1' then
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rd_cnt <= (others => '0');
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rd_en <= '1';
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end if;
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-- input read enable
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if rd_en = '1' then
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if rd_cnt = 64-1 then
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rd_cnt <= (others => '0');
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rd_en <= '0';
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else
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rd_cnt <= rd_cnt + 1;
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end if;
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end if;
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-- input data valid
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-- input data valid
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if divalid = '1' and zrl_proc_d1 = '0' then
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if divalid = '1' then
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wr_cnt <= wr_cnt + 1;
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wr_cnt <= wr_cnt + 1;
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-- first DCT coefficient received, DC data
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-- first DCT coefficient received, DC data
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if wr_cnt = 0 then
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if wr_cnt = 0 then
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-- differental coding of DC data per component
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-- differental coding of DC data per component
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| Line 189... |
Line 177... |
zero_cnt <= zero_cnt - 16;
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zero_cnt <= zero_cnt - 16;
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dovalid_reg <= '1';
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dovalid_reg <= '1';
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-- stall input until ZRL is handled
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-- stall input until ZRL is handled
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zrl_proc <= '1';
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zrl_proc <= '1';
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zrl_di <= di;
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zrl_di <= di;
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divalid <= '0';
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rd_cnt <= rd_cnt;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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-- ZRL processing
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-- ZRL processing
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if zrl_proc = '1' then
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if zrl_proc = '1' then
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if zero_cnt <= 15 then
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if zero_cnt <= 15 then
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acc_reg <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);
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acc_reg <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);
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runlength_reg <= zero_cnt(3 downto 0);
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runlength_reg <= zero_cnt(3 downto 0);
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if signed(di) = 0 then
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if signed(zrl_di) = 0 then
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zero_cnt <= to_unsigned(1,zero_cnt'length);
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zero_cnt <= to_unsigned(1,zero_cnt'length);
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else
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else
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zero_cnt <= (others => '0');
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zero_cnt <= (others => '0');
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end if;
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end if;
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dovalid_reg <= '1';
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dovalid_reg <= '1';
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divalid <= '1';
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-- continue input handling
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-- continue input handling
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zrl_proc <= '0';
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zrl_proc <= '0';
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-- zero_cnt > 15
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-- zero_cnt > 15
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else
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else
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-- generate ZRL
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-- generate ZRL
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acc_reg <= (others => '0');
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acc_reg <= (others => '0');
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runlength_reg <= X"F";
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runlength_reg <= X"F";
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zero_cnt <= zero_cnt - 16;
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zero_cnt <= zero_cnt - 16;
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dovalid_reg <= '1';
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dovalid_reg <= '1';
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divalid <= '0';
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rd_cnt <= rd_cnt;
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end if;
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end if;
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end if;
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end if;
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-- start of 8x8 block processing
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-- start of 8x8 block processing
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if start_pb = '1' then
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if start_pb = '1' then
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