| Line 60... |
Line 60... |
constant ZEROS_32_C : UNSIGNED(31 downto 0) := (others => '0');
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constant ZEROS_32_C : UNSIGNED(31 downto 0) := (others => '0');
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signal prev_dc_reg_0 : SIGNED(RAMDATA_W-1 downto 0);
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signal prev_dc_reg_0 : SIGNED(RAMDATA_W-1 downto 0);
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signal prev_dc_reg_1 : SIGNED(RAMDATA_W-1 downto 0);
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signal prev_dc_reg_1 : SIGNED(RAMDATA_W-1 downto 0);
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signal prev_dc_reg_2 : SIGNED(RAMDATA_W-1 downto 0);
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signal prev_dc_reg_2 : SIGNED(RAMDATA_W-1 downto 0);
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signal prev_dc_reg_3 : SIGNED(RAMDATA_W-1 downto 0);
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signal acc_reg : SIGNED(RAMDATA_W downto 0);
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signal acc_reg : SIGNED(RAMDATA_W downto 0);
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signal size_reg : UNSIGNED(SIZE_REG_C-1 downto 0);
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signal size_reg : UNSIGNED(SIZE_REG_C-1 downto 0);
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signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0);
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signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0);
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signal runlength_reg : UNSIGNED(3 downto 0);
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signal runlength_reg : UNSIGNED(3 downto 0);
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signal dovalid_reg : STD_LOGIC;
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signal dovalid_reg : STD_LOGIC;
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| Line 93... |
Line 94... |
if rst = '1' then
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if rst = '1' then
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wr_cnt_d1 <= (others => '0');
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wr_cnt_d1 <= (others => '0');
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prev_dc_reg_0 <= (others => '0');
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prev_dc_reg_0 <= (others => '0');
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prev_dc_reg_1 <= (others => '0');
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prev_dc_reg_1 <= (others => '0');
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prev_dc_reg_2 <= (others => '0');
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prev_dc_reg_2 <= (others => '0');
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prev_dc_reg_3 <= (others => '0');
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dovalid_reg <= '0';
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dovalid_reg <= '0';
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acc_reg <= (others => '0');
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acc_reg <= (others => '0');
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runlength_reg <= (others => '0');
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runlength_reg <= (others => '0');
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runlength <= (others => '0');
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runlength <= (others => '0');
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dovalid <= '0';
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dovalid <= '0';
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| Line 139... |
Line 141... |
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-- first DCT coefficient received, DC data
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-- first DCT coefficient received, DC data
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if wr_cnt = 0 then
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if wr_cnt = 0 then
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-- differental coding of DC data per component
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-- differental coding of DC data per component
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case rle_sm_settings.cmp_idx is
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case rle_sm_settings.cmp_idx is
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when "00" =>
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when "000" | "001" =>
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acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);
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acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);
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prev_dc_reg_0 <= SIGNED(di);
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prev_dc_reg_0 <= SIGNED(di);
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when "01" =>
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when "010" =>
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acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);
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acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);
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prev_dc_reg_1 <= SIGNED(di);
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prev_dc_reg_1 <= SIGNED(di);
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when "10" =>
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when "011" =>
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acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);
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acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);
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prev_dc_reg_2 <= SIGNED(di);
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prev_dc_reg_2 <= SIGNED(di);
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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| Line 227... |
Line 229... |
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if sof = '1' then
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if sof = '1' then
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prev_dc_reg_0 <= (others => '0');
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prev_dc_reg_0 <= (others => '0');
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prev_dc_reg_1 <= (others => '0');
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prev_dc_reg_1 <= (others => '0');
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prev_dc_reg_2 <= (others => '0');
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prev_dc_reg_2 <= (others => '0');
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prev_dc_reg_3 <= (others => '0');
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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