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[/] [mkjpeg/] [trunk/] [design/] [rle/] [RLE.VHD] - Diff between revs 41 and 61

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Rev 41 Rev 61
Line 60... Line 60...
  constant ZEROS_32_C      : UNSIGNED(31 downto 0) := (others => '0');
  constant ZEROS_32_C      : UNSIGNED(31 downto 0) := (others => '0');
 
 
  signal prev_dc_reg_0   : SIGNED(RAMDATA_W-1 downto 0);
  signal prev_dc_reg_0   : SIGNED(RAMDATA_W-1 downto 0);
  signal prev_dc_reg_1   : SIGNED(RAMDATA_W-1 downto 0);
  signal prev_dc_reg_1   : SIGNED(RAMDATA_W-1 downto 0);
  signal prev_dc_reg_2   : SIGNED(RAMDATA_W-1 downto 0);
  signal prev_dc_reg_2   : SIGNED(RAMDATA_W-1 downto 0);
 
  signal prev_dc_reg_3   : SIGNED(RAMDATA_W-1 downto 0);
  signal acc_reg         : SIGNED(RAMDATA_W downto 0);
  signal acc_reg         : SIGNED(RAMDATA_W downto 0);
  signal size_reg        : UNSIGNED(SIZE_REG_C-1 downto 0);
  signal size_reg        : UNSIGNED(SIZE_REG_C-1 downto 0);
  signal ampli_vli_reg   : SIGNED(RAMDATA_W downto 0);
  signal ampli_vli_reg   : SIGNED(RAMDATA_W downto 0);
  signal runlength_reg   : UNSIGNED(3 downto 0);
  signal runlength_reg   : UNSIGNED(3 downto 0);
  signal dovalid_reg     : STD_LOGIC;
  signal dovalid_reg     : STD_LOGIC;
Line 93... Line 94...
    if rst = '1' then
    if rst = '1' then
      wr_cnt_d1       <= (others => '0');
      wr_cnt_d1       <= (others => '0');
      prev_dc_reg_0   <= (others => '0');
      prev_dc_reg_0   <= (others => '0');
      prev_dc_reg_1   <= (others => '0');
      prev_dc_reg_1   <= (others => '0');
      prev_dc_reg_2   <= (others => '0');
      prev_dc_reg_2   <= (others => '0');
 
      prev_dc_reg_3   <= (others => '0');
      dovalid_reg     <= '0';
      dovalid_reg     <= '0';
      acc_reg         <= (others => '0');
      acc_reg         <= (others => '0');
      runlength_reg   <= (others => '0');
      runlength_reg   <= (others => '0');
      runlength       <= (others => '0');
      runlength       <= (others => '0');
      dovalid         <= '0';
      dovalid         <= '0';
Line 139... Line 141...
 
 
        -- first DCT coefficient received, DC data
        -- first DCT coefficient received, DC data
        if wr_cnt = 0 then
        if wr_cnt = 0 then
          -- differental coding of DC data per component
          -- differental coding of DC data per component
          case rle_sm_settings.cmp_idx is
          case rle_sm_settings.cmp_idx is
            when "00" =>
            when "000" | "001" =>
              acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);
              acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);
              prev_dc_reg_0 <= SIGNED(di);
              prev_dc_reg_0 <= SIGNED(di);
            when "01" =>
            when "010" =>
              acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);
              acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);
              prev_dc_reg_1 <= SIGNED(di);
              prev_dc_reg_1 <= SIGNED(di);
            when "10" =>
            when "011" =>
              acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);
              acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);
              prev_dc_reg_2 <= SIGNED(di);
              prev_dc_reg_2 <= SIGNED(di);
            when others =>
            when others =>
              null;
              null;
          end case;
          end case;
Line 227... Line 229...
 
 
      if sof = '1' then
      if sof = '1' then
        prev_dc_reg_0 <= (others => '0');
        prev_dc_reg_0 <= (others => '0');
        prev_dc_reg_1 <= (others => '0');
        prev_dc_reg_1 <= (others => '0');
        prev_dc_reg_2 <= (others => '0');
        prev_dc_reg_2 <= (others => '0');
 
        prev_dc_reg_3 <= (others => '0');
      end if;
      end if;
 
 
    end if;
    end if;
  end process;
  end process;
 
 

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