| Line 58... |
Line 58... |
huf_size : out std_logic_vector(3 downto 0);
|
huf_size : out std_logic_vector(3 downto 0);
|
huf_amplitude : out std_logic_vector(11 downto 0);
|
huf_amplitude : out std_logic_vector(11 downto 0);
|
huf_dval : out std_logic;
|
huf_dval : out std_logic;
|
huf_fifo_empty : out std_logic;
|
huf_fifo_empty : out std_logic;
|
|
|
-- ZIGZAG
|
-- Quantizer
|
zig_buf_sel : out std_logic;
|
qua_buf_sel : out std_logic;
|
zig_rd_addr : out std_logic_vector(5 downto 0);
|
qua_rd_addr : out std_logic_vector(5 downto 0);
|
zig_data : in std_logic_vector(11 downto 0);
|
qua_data : in std_logic_vector(11 downto 0);
|
|
|
-- HostIF
|
-- HostIF
|
sof : in std_logic
|
sof : in std_logic
|
);
|
);
|
end entity RLE_TOP;
|
end entity RLE_TOP;
|
| Line 90... |
Line 90... |
signal rle_amplitude : std_logic_vector(11 downto 0);
|
signal rle_amplitude : std_logic_vector(11 downto 0);
|
signal rle_dovalid : std_logic;
|
signal rle_dovalid : std_logic;
|
signal rle_di : std_logic_vector(11 downto 0);
|
signal rle_di : std_logic_vector(11 downto 0);
|
signal rle_divalid : std_logic;
|
signal rle_divalid : std_logic;
|
|
|
signal zig_buf_sel_s : std_logic;
|
signal qua_buf_sel_s : std_logic;
|
signal huf_dval_p0 : std_logic;
|
signal huf_dval_p0 : std_logic;
|
|
|
signal wr_cnt : unsigned(5 downto 0);
|
signal wr_cnt : unsigned(5 downto 0);
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Architecture: begin
|
-- Architecture: begin
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
begin
|
begin
|
|
|
zig_rd_addr <= std_logic_vector(rd_cnt);
|
qua_rd_addr <= std_logic_vector(rd_cnt);
|
huf_runlength <= dbuf_q(19 downto 16);
|
huf_runlength <= dbuf_q(19 downto 16);
|
huf_size <= dbuf_q(15 downto 12);
|
huf_size <= dbuf_q(15 downto 12);
|
huf_amplitude <= dbuf_q(11 downto 0);
|
huf_amplitude <= dbuf_q(11 downto 0);
|
zig_buf_sel <= zig_buf_sel_s;
|
qua_buf_sel <= qua_buf_sel_s;
|
|
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
-- RLE Core
|
-- RLE Core
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
U_rle : entity work.rle
|
U_rle : entity work.rle
|
| Line 131... |
Line 131... |
size => rle_size,
|
size => rle_size,
|
amplitude => rle_amplitude,
|
amplitude => rle_amplitude,
|
dovalid => rle_dovalid
|
dovalid => rle_dovalid
|
);
|
);
|
|
|
rle_di <= zig_data;
|
rle_di <= qua_data;
|
rle_divalid <= rd_en_d(0);
|
rle_divalid <= rd_en_d(0);
|
|
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
-- Double Fifo
|
-- Double Fifo
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
| Line 228... |
Line 228... |
-- fdct_buf_sel
|
-- fdct_buf_sel
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
p_buf_sel : process(CLK, RST)
|
p_buf_sel : process(CLK, RST)
|
begin
|
begin
|
if RST = '1' then
|
if RST = '1' then
|
zig_buf_sel_s <= '0';
|
qua_buf_sel_s <= '0';
|
elsif CLK'event and CLK = '1' then
|
elsif CLK'event and CLK = '1' then
|
if start_pb = '1' then
|
if start_pb = '1' then
|
zig_buf_sel_s <= not zig_buf_sel_s;
|
qua_buf_sel_s <= not qua_buf_sel_s;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
