| Line 79... |
Line 79... |
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signal dbuf_data : std_logic_vector(19 downto 0);
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signal dbuf_data : std_logic_vector(19 downto 0);
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signal dbuf_q : std_logic_vector(19 downto 0);
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signal dbuf_q : std_logic_vector(19 downto 0);
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signal dbuf_we : std_logic;
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signal dbuf_we : std_logic;
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signal rd_cnt : unsigned(5 downto 0);
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signal rd_en_d : std_logic_vector(5 downto 0);
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signal rd_en : std_logic;
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signal rle_runlength : std_logic_vector(3 downto 0);
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signal rle_runlength : std_logic_vector(3 downto 0);
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signal rle_size : std_logic_vector(3 downto 0);
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signal rle_size : std_logic_vector(3 downto 0);
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signal rle_amplitude : std_logic_vector(11 downto 0);
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signal rle_amplitude : std_logic_vector(11 downto 0);
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signal rle_dovalid : std_logic;
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signal rle_dovalid : std_logic;
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signal rle_di : std_logic_vector(11 downto 0);
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signal rle_di : std_logic_vector(11 downto 0);
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| Line 100... |
Line 96... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture: begin
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-- Architecture: begin
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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begin
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begin
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qua_rd_addr <= std_logic_vector(rd_cnt);
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huf_runlength <= dbuf_q(19 downto 16);
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huf_runlength <= dbuf_q(19 downto 16);
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huf_size <= dbuf_q(15 downto 12);
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huf_size <= dbuf_q(15 downto 12);
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huf_amplitude <= dbuf_q(11 downto 0);
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huf_amplitude <= dbuf_q(11 downto 0);
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qua_buf_sel <= qua_buf_sel_s;
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qua_buf_sel <= qua_buf_sel_s;
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| Line 120... |
Line 115... |
port map
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port map
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(
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(
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rst => RST,
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rst => RST,
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clk => CLK,
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clk => CLK,
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di => rle_di,
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di => rle_di,
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divalid => rle_divalid,
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start_pb => start_pb,
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start_pb => start_pb,
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sof => sof,
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sof => sof,
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rle_sm_settings => rle_sm_settings,
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rle_sm_settings => rle_sm_settings,
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runlength => rle_runlength,
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runlength => rle_runlength,
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size => rle_size,
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size => rle_size,
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amplitude => rle_amplitude,
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amplitude => rle_amplitude,
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dovalid => rle_dovalid
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dovalid => rle_dovalid,
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rd_addr => qua_rd_addr
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);
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);
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rle_di <= qua_data;
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rle_di <= qua_data;
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rle_divalid <= rd_en_d(0);
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- Double Fifo
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-- Double Fifo
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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U_RleDoubleFifo : entity work.RleDoubleFifo
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U_RleDoubleFifo : entity work.RleDoubleFifo
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| Line 155... |
Line 149... |
);
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);
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dbuf_data <= rle_runlength & rle_size & rle_amplitude;
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dbuf_data <= rle_runlength & rle_size & rle_amplitude;
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dbuf_we <= rle_dovalid;
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dbuf_we <= rle_dovalid;
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-------------------------------------------------------------------
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-- Counter1
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-------------------------------------------------------------------
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p_counter1 : process(CLK, RST)
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begin
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if RST = '1' then
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rd_en <= '0';
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rd_en_d <= (others => '0');
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rd_cnt <= (others => '0');
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elsif CLK'event and CLK = '1' then
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rd_en_d <= rd_en_d(rd_en_d'length-2 downto 0) & rd_en;
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if start_pb = '1' then
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rd_cnt <= (others => '0');
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rd_en <= '1';
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end if;
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if rd_en = '1' then
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if rd_cnt = 64-1 then
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rd_cnt <= (others => '0');
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rd_en <= '0';
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else
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rd_cnt <= rd_cnt + 1;
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end if;
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end if;
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end if;
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end process;
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- ready_pb
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-- ready_pb
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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p_ready_pb : process(CLK, RST)
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p_ready_pb : process(CLK, RST)
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