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[/] [mkjpeg/] [trunk/] [design/] [rle/] [RleDoubleFifo.vhd] - Diff between revs 25 and 38
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| Rev 25 |
Rev 38 |
| Line 152... |
Line 152... |
-- mux3
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-- mux3
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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p_mux3 : process(CLK, RST)
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p_mux3 : process(CLK, RST)
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begin
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begin
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if RST = '1' then
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if RST = '1' then
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data_out <= (others => '0');
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--data_out <= (others => '0');
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fifo1_rd <= '0';
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--fifo1_rd <= '0';
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fifo2_rd <= '0';
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--fifo2_rd <= '0';
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fifo_empty <= '0';
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--fifo_empty <= '0';
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elsif CLK'event and CLK = '1' then
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elsif CLK'event and CLK = '1' then
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if buf_sel = '1' then
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if buf_sel = '1' then
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data_out <= fifo1_q;
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--data_out <= fifo1_q;
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fifo1_rd <= rd_req;
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--fifo1_rd <= rd_req;
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fifo_empty <= fifo1_empty;
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--fifo_empty <= fifo1_empty;
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else
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else
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data_out <= fifo2_q;
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--data_out <= fifo2_q;
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fifo2_rd <= rd_req;
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--fifo2_rd <= rd_req;
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fifo_empty <= fifo2_empty;
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--fifo_empty <= fifo2_empty;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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fifo1_rd <= rd_req when buf_sel = '1' else '0';
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fifo2_rd <= rd_req when buf_sel = '0' else '0';
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data_out <= fifo1_q when buf_sel = '1' else fifo2_q;
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fifo_empty <= fifo1_empty when buf_sel = '1' else fifo2_empty;
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end architecture RTL;
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end architecture RTL;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture: end
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-- Architecture: end
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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