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[/] [mkjpeg/] [trunk/] [design/] [rle/] [RleDoubleFifo.vhd] - Diff between revs 25 and 38

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Rev 25 Rev 38
Line 152... Line 152...
  -- mux3
  -- mux3
  -------------------------------------------------------------------
  -------------------------------------------------------------------
  p_mux3 : process(CLK, RST)
  p_mux3 : process(CLK, RST)
  begin
  begin
    if RST = '1' then
    if RST = '1' then
      data_out   <= (others => '0');
      --data_out   <= (others => '0');
      fifo1_rd   <= '0';
      --fifo1_rd   <= '0';
      fifo2_rd   <= '0';
      --fifo2_rd   <= '0';
      fifo_empty <= '0';
      --fifo_empty <= '0';
    elsif CLK'event and CLK = '1' then
    elsif CLK'event and CLK = '1' then
      if buf_sel = '1' then
      if buf_sel = '1' then
        data_out   <= fifo1_q;
        --data_out   <= fifo1_q;
        fifo1_rd   <= rd_req;
        --fifo1_rd   <= rd_req;
        fifo_empty <= fifo1_empty;
        --fifo_empty <= fifo1_empty;
      else
      else
        data_out <= fifo2_q;
        --data_out <= fifo2_q;
        fifo2_rd <= rd_req;
        --fifo2_rd <= rd_req;
        fifo_empty <= fifo2_empty;
        --fifo_empty <= fifo2_empty;
      end if;
      end if;
    end if;
    end if;
  end process;
  end process;
 
 
 
  fifo1_rd   <= rd_req when buf_sel = '1' else '0';
 
  fifo2_rd   <= rd_req when buf_sel = '0' else '0';
 
 
 
  data_out   <= fifo1_q when buf_sel = '1' else fifo2_q;
 
  fifo_empty   <= fifo1_empty when buf_sel = '1' else fifo2_empty;
 
 
 
 
 
 
end architecture RTL;
end architecture RTL;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Architecture: end
-- Architecture: end
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
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