URL https://opencores.org/ocsvn/mkjpeg/mkjpeg/trunk

Subversion Repositories mkjpeg

[/] [mkjpeg/] [trunk/] [design/] [top/] [JpegEnc.vhd] - Diff between revs 25 and 32

Rev 25	Rev 32
Line 77...	Line 77...
`-------------------------------------------------------------------------------`	`-------------------------------------------------------------------------------`
`-------------------------------------------------------------------------------`	`-------------------------------------------------------------------------------`
`architecture RTL of JpegEnc is`	`architecture RTL of JpegEnc is`

`signal qdata : std_logic_vector(7 downto 0);`	`signal qdata : std_logic_vector(7 downto 0);`
`signal qaddr : std_logic_vector(5 downto 0);`	`signal qaddr : std_logic_vector(6 downto 0);`
`signal qwren : std_logic;`	`signal qwren : std_logic;`
`signal jpeg_ready : std_logic;`	`signal jpeg_ready : std_logic;`
`signal jpeg_busy : std_logic;`	`signal jpeg_busy : std_logic;`
`signal outram_base_addr : std_logic_vector(9 downto 0);`	`signal outram_base_addr : std_logic_vector(9 downto 0);`
`signal num_enc_bytes : std_logic_vector(23 downto 0);`	`signal num_enc_bytes : std_logic_vector(23 downto 0);`
Line 308...	Line 308...
`CLK => CLK,`	`CLK => CLK,`
`RST => RST,`	`RST => RST,`
`-- CTRL`	`-- CTRL`
`start_pb => zig_start,`	`start_pb => zig_start,`
`ready_pb => zig_ready,`	`ready_pb => zig_ready,`
	`zig_sm_settings => zig_sm_settings,`

`-- RLE`	`-- RLE`
`rle_buf_sel => rle_buf_sel,`	`rle_buf_sel => rle_buf_sel,`
`rle_rdaddr => rle_rdaddr,`	`rle_rdaddr => rle_rdaddr,`
`rle_data => rle_data,`	`rle_data => rle_data,`