OpenCores
URL https://opencores.org/ocsvn/mkjpeg/mkjpeg/trunk

Subversion Repositories mkjpeg

[/] [mkjpeg/] [trunk/] [design/] [zigzag/] [ZZ_TOP.VHD] - Diff between revs 32 and 34

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 32 Rev 34
Line 5... Line 5...
--
--
-- Module    : ZZ_TOP
-- Module    : ZZ_TOP
--
--
-- Content   : ZigZag Top level
-- Content   : ZigZag Top level
--
--
-- Description : Zig Zag scan and Quantizer
-- Description : Zig Zag scan
--
--
-- Spec.     :
-- Spec.     :
--
--
-- Author    : Michal Krepa
-- Author    : Michal Krepa
--
--
Line 49... Line 49...
        -- CTRL
        -- CTRL
        start_pb           : in  std_logic;
        start_pb           : in  std_logic;
        ready_pb           : out std_logic;
        ready_pb           : out std_logic;
        zig_sm_settings    : in  T_SM_SETTINGS;
        zig_sm_settings    : in  T_SM_SETTINGS;
 
 
        -- RLE
        -- Quantizer
        rle_buf_sel        : in  std_logic;
        qua_buf_sel        : in  std_logic;
        rle_rdaddr         : in  std_logic_vector(5 downto 0);
        qua_rdaddr         : in  std_logic_vector(5 downto 0);
        rle_data           : out std_logic_vector(11 downto 0);
        qua_data           : out std_logic_vector(11 downto 0);
 
 
        -- FDCT
        -- FDCT
        fdct_buf_sel       : out std_logic;
        fdct_buf_sel       : out std_logic;
        fdct_rd_addr       : out std_logic_vector(5 downto 0);
        fdct_rd_addr       : out std_logic_vector(5 downto 0);
        fdct_data          : in  std_logic_vector(11 downto 0);
        fdct_data          : in  std_logic_vector(11 downto 0);
        fdct_rden          : out std_logic;
        fdct_rden          : out std_logic
 
 
        -- HOST
 
        qdata              : in  std_logic_vector(7 downto 0);
 
        qaddr              : in  std_logic_vector(6 downto 0);
 
        qwren              : in  std_logic
 
    );
    );
end entity ZZ_TOP;
end entity ZZ_TOP;
 
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
Line 83... Line 78...
  signal dbuf_raddr     : std_logic_vector(6 downto 0);
  signal dbuf_raddr     : std_logic_vector(6 downto 0);
  signal zigzag_di      : std_logic_vector(11 downto 0);
  signal zigzag_di      : std_logic_vector(11 downto 0);
  signal zigzag_divalid : std_logic;
  signal zigzag_divalid : std_logic;
  signal zigzag_dout    : std_logic_vector(11 downto 0);
  signal zigzag_dout    : std_logic_vector(11 downto 0);
  signal zigzag_dovalid : std_logic;
  signal zigzag_dovalid : std_logic;
  signal quant_dout     : std_logic_vector(11 downto 0);
 
  signal quant_dovalid  : std_logic;
 
  signal wr_cnt         : unsigned(5 downto 0);
  signal wr_cnt         : unsigned(5 downto 0);
  signal rd_cnt         : unsigned(5 downto 0);
  signal rd_cnt         : unsigned(5 downto 0);
  signal rd_en_d        : std_logic_vector(5 downto 0);
  signal rd_en_d        : std_logic_vector(5 downto 0);
  signal rd_en          : std_logic;
  signal rd_en          : std_logic;
  signal fdct_buf_sel_s : std_logic;
  signal fdct_buf_sel_s : std_logic;
Line 100... Line 93...
-- Architecture: begin
-- Architecture: begin
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
begin
begin
 
 
  fdct_rd_addr <= std_logic_vector(zz_rd_addr);
  fdct_rd_addr <= std_logic_vector(zz_rd_addr);
  rle_data     <= dbuf_q;
  qua_data     <= dbuf_q;
  fdct_buf_sel <= fdct_buf_sel_s;
  fdct_buf_sel <= fdct_buf_sel_s;
  fdct_rden    <= rd_en;
  fdct_rden    <= rd_en;
 
 
  -------------------------------------------------------------------
  -------------------------------------------------------------------
  -- ZigZag Core
  -- ZigZag Core
Line 132... Line 125...
 
 
  zigzag_di      <= fdct_data;
  zigzag_di      <= fdct_data;
  zigzag_divalid <= rd_en_d(1);
  zigzag_divalid <= rd_en_d(1);
 
 
  -------------------------------------------------------------------
  -------------------------------------------------------------------
  -- Quantizer
 
  -------------------------------------------------------------------
 
  U_quantizer : entity work.quantizer
 
  generic map
 
    (
 
      SIZE_C        => 12,
 
      RAMQADDR_W    => 7,
 
      RAMQDATA_W    => 8
 
    )
 
  port map
 
    (
 
      rst      => RST,
 
      clk      => CLK,
 
      di       => zigzag_dout,
 
      divalid  => zigzag_dovalid,
 
      qdata    => qdata,
 
      qwaddr   => qaddr,
 
      qwren    => qwren,
 
      cmp_idx  => zig_sm_settings.cmp_idx,
 
 
 
      do       => quant_dout,
 
      dovalid  => quant_dovalid
 
    );
 
 
 
  -------------------------------------------------------------------
 
  -- DBUF
  -- DBUF
  -------------------------------------------------------------------
  -------------------------------------------------------------------
  U_RAMZ : entity work.RAMZ
  U_RAMZ : entity work.RAMZ
  generic map
  generic map
  (
  (
Line 176... Line 144...
        clk         => CLK,
        clk         => CLK,
 
 
        q           => dbuf_q
        q           => dbuf_q
  );
  );
 
 
  dbuf_data  <= quant_dout;
  dbuf_data  <= zigzag_dout;
  dbuf_waddr <= (not rle_buf_sel) & std_logic_vector(wr_cnt);
  dbuf_waddr <= (not qua_buf_sel) & std_logic_vector(wr_cnt);
  dbuf_we    <= quant_dovalid;
  dbuf_we    <= zigzag_dovalid;
  dbuf_raddr <= rle_buf_sel & rle_rdaddr;
  dbuf_raddr <= qua_buf_sel & qua_rdaddr;
 
 
  -------------------------------------------------------------------
  -------------------------------------------------------------------
  -- FIFO Ctrl
  -- FIFO Ctrl
  -------------------------------------------------------------------
  -------------------------------------------------------------------
  p_fifo_ctrl : process(CLK, RST)
  p_fifo_ctrl : process(CLK, RST)
Line 241... Line 209...
 
 
      if start_pb = '1' then
      if start_pb = '1' then
        wr_cnt <= (others => '0');
        wr_cnt <= (others => '0');
      end if;
      end if;
 
 
      if quant_dovalid = '1' then
      if zigzag_dovalid = '1' then
        if wr_cnt = 64-1 then
        if wr_cnt = 64-1 then
          wr_cnt <= (others => '0');
          wr_cnt <= (others => '0');
          ready_pb <= '1';
 
        else
        else
          wr_cnt <=wr_cnt + 1;
          wr_cnt <=wr_cnt + 1;
        end if;
        end if;
 
 
 
        -- give ready ahead to save cycles!
 
        if wr_cnt = 64-1-3 then
 
          ready_pb <= '1';
 
        end if;
 
 
      end if;
      end if;
    end if;
    end if;
  end process;
  end process;
 
 
  -------------------------------------------------------------------
  -------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.