| Line 226... |
Line 226... |
pc_out : out std_logic_vector(31 downto 0);
|
pc_out : out std_logic_vector(31 downto 0);
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pc_out_plus4 : out std_logic_vector(31 downto 0));
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pc_out_plus4 : out std_logic_vector(31 downto 0));
|
end component;
|
end component;
|
|
|
component mem_ctrl
|
component mem_ctrl
|
|
generic(ACCURATE_TIMING : boolean := false);
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
pause_in : in std_logic;
|
pause_in : in std_logic;
|
nullify_op : in std_logic;
|
nullify_op : in std_logic;
|
address_pc : in std_logic_vector(31 downto 0);
|
address_pc : in std_logic_vector(31 downto 0);
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| Line 243... |
Line 244... |
|
|
mem_address : out std_logic_vector(31 downto 0);
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mem_address : out std_logic_vector(31 downto 0);
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mem_data_w : out std_logic_vector(31 downto 0);
|
mem_data_w : out std_logic_vector(31 downto 0);
|
mem_data_r : in std_logic_vector(31 downto 0);
|
mem_data_r : in std_logic_vector(31 downto 0);
|
mem_byte_sel : out std_logic_vector(3 downto 0);
|
mem_byte_sel : out std_logic_vector(3 downto 0);
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mem_write : out std_logic;
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mem_write : out std_logic);
|
mem_pause : in std_logic);
|
|
end component;
|
end component;
|
|
|
component control
|
component control
|
port(opcode : in std_logic_vector(31 downto 0);
|
port(opcode : in std_logic_vector(31 downto 0);
|
intr_signal : in std_logic;
|
intr_signal : in std_logic;
|
pause_in : in std_logic;
|
|
rs_index : out std_logic_vector(5 downto 0);
|
rs_index : out std_logic_vector(5 downto 0);
|
rt_index : out std_logic_vector(5 downto 0);
|
rt_index : out std_logic_vector(5 downto 0);
|
rd_index : out std_logic_vector(5 downto 0);
|
rd_index : out std_logic_vector(5 downto 0);
|
imm_out : out std_logic_vector(15 downto 0);
|
imm_out : out std_logic_vector(15 downto 0);
|
alu_func : out alu_function_type;
|
alu_func : out alu_function_type;
|
| Line 270... |
Line 269... |
|
|
component reg_bank
|
component reg_bank
|
generic(memory_type : string := "TRI_PORT");
|
generic(memory_type : string := "TRI_PORT");
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
|
pause : in std_logic;
|
rs_index : in std_logic_vector(5 downto 0);
|
rs_index : in std_logic_vector(5 downto 0);
|
rt_index : in std_logic_vector(5 downto 0);
|
rt_index : in std_logic_vector(5 downto 0);
|
rd_index : in std_logic_vector(5 downto 0);
|
rd_index : in std_logic_vector(5 downto 0);
|
reg_source_out : out std_logic_vector(31 downto 0);
|
reg_source_out : out std_logic_vector(31 downto 0);
|
reg_target_out : out std_logic_vector(31 downto 0);
|
reg_target_out : out std_logic_vector(31 downto 0);
|
| Line 324... |
Line 324... |
mult_func : in mult_function_type;
|
mult_func : in mult_function_type;
|
c_mult : out std_logic_vector(31 downto 0);
|
c_mult : out std_logic_vector(31 downto 0);
|
pause_out : out std_logic);
|
pause_out : out std_logic);
|
end component;
|
end component;
|
|
|
|
component pipeline
|
|
port(clk : in std_logic;
|
|
reset : in std_logic;
|
|
a_bus : in std_logic_vector(31 downto 0);
|
|
a_busD : out std_logic_vector(31 downto 0);
|
|
b_bus : in std_logic_vector(31 downto 0);
|
|
b_busD : out std_logic_vector(31 downto 0);
|
|
alu_func : in alu_function_type;
|
|
alu_funcD : out alu_function_type;
|
|
shift_func : in shift_function_type;
|
|
shift_funcD : out shift_function_type;
|
|
mult_func : in mult_function_type;
|
|
mult_funcD : out mult_function_type;
|
|
reg_dest : in std_logic_vector(31 downto 0);
|
|
reg_destD : out std_logic_vector(31 downto 0);
|
|
rd_index : in std_logic_vector(5 downto 0);
|
|
rd_indexD : out std_logic_vector(5 downto 0);
|
|
|
|
rs_index : in std_logic_vector(5 downto 0);
|
|
rt_index : in std_logic_vector(5 downto 0);
|
|
pc_source : in pc_source_type;
|
|
mem_source : in mem_source_type;
|
|
a_source : in a_source_type;
|
|
b_source : in b_source_type;
|
|
c_source : in c_source_type;
|
|
c_bus : in std_logic_vector(31 downto 0);
|
|
take_branch : in std_logic;
|
|
take_branchD : out std_logic;
|
|
pause_any : in std_logic;
|
|
pause_pipeline : out std_logic);
|
|
end component;
|
|
|
component mlite_cpu
|
component mlite_cpu
|
generic(memory_type : string := "ALTERA");
|
generic(memory_type : string := "ALTERA";
|
|
pipeline_stages : natural := 3);
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
intr_in : in std_logic;
|
intr_in : in std_logic;
|
|
|
mem_address : out std_logic_vector(31 downto 0);
|
mem_address : out std_logic_vector(31 downto 0);
|
