| Line 96... |
Line 96... |
signal pause : std_logic;
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signal pause : std_logic;
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signal nullify_op : std_logic;
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signal nullify_op : std_logic;
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signal intr_enable : std_logic;
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signal intr_enable : std_logic;
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signal intr_signal : std_logic;
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signal intr_signal : std_logic;
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signal reset_reg : std_logic;
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signal reset_reg : std_logic;
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signal reset : std_logic;
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begin --architecture
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begin --architecture
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pause <= pause_mult or pause_memory;
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pause <= pause_mult or pause_memory;
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nullify_op <= '1' when pc_source = from_lbranch and
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nullify_op <= '1' when pc_source = from_lbranch and
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(take_branch = '0' or branch_function = branch_yes) else
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(take_branch = '0' or branch_function = branch_yes) else
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'0';
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'0';
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c_bus <= c_alu or c_shift or c_mult;
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c_bus <= c_alu or c_shift or c_mult;
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reset <= reset_in or reset_reg;
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--synchronize reset and interrupt pins
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--synchronize reset and interrupt pins
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intr_proc: process(clk, reset_in, intr_in, intr_enable, pc_source, pc, pause)
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intr_proc: process(clk, reset_in, intr_in, intr_enable, pc_source, pc, pause)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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| Line 124... |
Line 126... |
end if;
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end if;
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end process;
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end process;
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u1_pc_next: pc_next PORT MAP (
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u1_pc_next: pc_next PORT MAP (
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clk => clk,
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clk => clk,
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reset_in => reset_reg,
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reset_in => reset,
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take_branch => take_branch,
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take_branch => take_branch,
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pause_in => pause,
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pause_in => pause,
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pc_new => c_alu(31 downto 2),
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pc_new => c_alu(31 downto 2),
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opcode25_0 => opcode(25 downto 0),
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opcode25_0 => opcode(25 downto 0),
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pc_source => pc_source,
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pc_source => pc_source,
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pc_out => pc,
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pc_out => pc,
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pc_out_plus4 => pc_plus4);
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pc_out_plus4 => pc_plus4);
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u2_mem_ctrl: mem_ctrl PORT MAP (
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u2_mem_ctrl: mem_ctrl PORT MAP (
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clk => clk,
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clk => clk,
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reset_in => reset_reg,
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reset_in => reset,
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pause_in => pause,
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pause_in => pause,
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nullify_op => nullify_op,
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nullify_op => nullify_op,
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address_pc => pc,
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address_pc => pc,
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opcode_out => opcode,
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opcode_out => opcode,
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| Line 176... |
Line 178... |
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u4_reg_bank: reg_bank
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u4_reg_bank: reg_bank
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generic map(memory_type => memory_type)
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generic map(memory_type => memory_type)
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port map (
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port map (
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clk => clk,
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clk => clk,
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reset_in => reset_reg,
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reset_in => reset,
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rs_index => rs_index,
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rs_index => rs_index,
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rt_index => rt_index,
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rt_index => rt_index,
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rd_index => rd_index,
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rd_index => rd_index,
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reg_source_out => reg_source,
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reg_source_out => reg_source,
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reg_target_out => reg_target,
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reg_target_out => reg_target,
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