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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity alu is
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entity alu is
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generic(adder_type : string := "GENERIC");
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generic(adder_type : string := "GENERIC";
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alu_type : string := "GENERIC");
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port(a_in : in std_logic_vector(31 downto 0);
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port(a_in : in std_logic_vector(31 downto 0);
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b_in : in std_logic_vector(31 downto 0);
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b_in : in std_logic_vector(31 downto 0);
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alu_function : in alu_function_type;
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alu_function : in alu_function_type;
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c_alu : out std_logic_vector(31 downto 0));
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c_alu : out std_logic_vector(31 downto 0));
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end; --alu
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end; --alu
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architecture logic of alu is
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architecture logic of alu is
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-- type alu_function_type is (alu_nothing, alu_add, alu_subtract,
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-- type alu_function_type is (alu_nothing, alu_add, alu_subtract,
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-- alu_less_than, alu_less_than_signed,
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-- alu_less_than, alu_less_than_signed,
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-- alu_or, alu_and, alu_xor, alu_nor);
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-- alu_or, alu_and, alu_xor, alu_nor);
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signal aa, bb, sum : std_logic_vector(32 downto 0);
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signal aa, bb, sum : std_logic_vector(32 downto 0);
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signal do_add : std_logic;
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signal do_add : std_logic;
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signal sign_ext : std_logic;
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begin
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begin
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alu_proc: process(a_in, b_in, alu_function, sum)
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do_add <= '1' when alu_function = alu_add else '0';
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variable sign_ext : std_logic;
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sign_ext <= '0' when alu_function = alu_less_than else '1';
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begin
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if alu_function = alu_add then
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do_add <= '1';
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else
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do_add <= '0';
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end if;
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if alu_function = alu_less_than then
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sign_ext := '0';
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else
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sign_ext := '1';
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end if;
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aa <= (a_in(31) and sign_ext) & a_in;
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aa <= (a_in(31) and sign_ext) & a_in;
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bb <= (b_in(31) and sign_ext) & b_in;
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bb <= (b_in(31) and sign_ext) & b_in;
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case alu_function is
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-- synthesis translate_off
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when alu_add | alu_subtract => --c=a+b
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GENERIC_ALU: if alu_type="GENERIC" generate
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c_alu <= sum(31 downto 0);
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-- synthesis translate_on
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when alu_less_than => --c=a<b
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c_alu <= ZERO(31 downto 1) & sum(32);
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c_alu <= sum(31 downto 0) when alu_function=alu_add or alu_function=alu_subtract else
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when alu_less_than_signed => --c=a<b;
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ZERO(31 downto 1) & sum(32) when alu_function=alu_less_than or alu_function=alu_less_than_signed else
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c_alu <= ZERO(31 downto 1) & sum(32);
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a_in or b_in when alu_function=alu_or else
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when alu_or => --c=a|b
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a_in and b_in when alu_function=alu_and else
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c_alu <= a_in or b_in;
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a_in xor b_in when alu_function=alu_xor else
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when alu_and => --c=a&b
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a_in nor b_in when alu_function=alu_nor else
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c_alu <= a_in and b_in;
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ZERO;
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when alu_xor => --c=a^b
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c_alu <= a_in xor b_in;
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-- synthesis translate_off
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when alu_nor => --c=~(a|b)
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end generate;
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c_alu <= a_in nor b_in;
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-- synthesis translate_on
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when others => --alu_function = alu_nothing
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c_alu <= ZERO;
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-- synopsys synthesis_off
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end case;
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AREA_OPTIMIZED_ALU: if alu_type="AREA_OPTIMIZED" generate
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c_alu <= sum(31 downto 0) when alu_function=alu_add or alu_function=alu_subtract else (others => 'Z');
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c_alu <= ZERO(31 downto 1) & sum(32) when alu_function=alu_less_than or alu_function=alu_less_than_signed else (others => 'Z');
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c_alu <= a_in or b_in when alu_function=alu_or else (others => 'Z');
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c_alu <= a_in and b_in when alu_function=alu_and else (others => 'Z');
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c_alu <= a_in xor b_in when alu_function=alu_xor else (others => 'Z');
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c_alu <= a_in nor b_in when alu_function=alu_nor else (others => 'Z');
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c_alu <= ZERO when alu_function=alu_nothing else (others => 'Z');
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end process;
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end generate;
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generic_adder: if adder_type = "GENERIC" generate
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generic_adder:
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if adder_type /= "ALTERA" generate
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sum <= bv_adder(aa, bb, do_add);
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sum <= bv_adder(aa, bb, do_add);
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end generate; --generic_adder
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end generate; --generic_adder
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--For Altera
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--For Altera
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lpm_adder:
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lpm_adder: if adder_type = "ALTERA" generate
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if adder_type = "ALTERA" generate
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lpm_add_sub_component : lpm_add_sub
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lpm_add_sub_component : lpm_add_sub
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GENERIC MAP (
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GENERIC MAP (
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lpm_width => 33,
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lpm_width => 33,
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lpm_direction => "UNUSED",
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lpm_direction => "UNUSED",
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lpm_type => "LPM_ADD_SUB",
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lpm_type => "LPM_ADD_SUB",
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datab => bb,
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datab => bb,
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result => sum
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result => sum
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);
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);
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end generate; --lpm_adder
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end generate; --lpm_adder
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-- synopsys synthesis_on
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end; --architecture logic
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end; --architecture logic
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