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alu_function : in alu_function_type;
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alu_function : in alu_function_type;
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c_alu : out std_logic_vector(31 downto 0));
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c_alu : out std_logic_vector(31 downto 0));
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end; --alu
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end; --alu
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architecture logic of alu is
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architecture logic of alu is
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-- type alu_function_type is (alu_nothing, alu_add, alu_subtract,
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-- alu_less_than, alu_less_than_signed,
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-- alu_or, alu_and, alu_xor, alu_nor);
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signal aa, bb, sum : std_logic_vector(32 downto 0);
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signal aa, bb, sum : std_logic_vector(32 downto 0);
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signal do_add : std_logic;
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signal do_add : std_logic;
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signal sign_ext : std_logic;
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signal sign_ext : std_logic;
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begin
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begin
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do_add <= '1' when alu_function = alu_add else '0';
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do_add <= '1' when alu_function = ALU_ADD else '0';
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sign_ext <= '0' when alu_function = alu_less_than else '1';
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sign_ext <= '0' when alu_function = ALU_LESS_THAN else '1';
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aa <= (a_in(31) and sign_ext) & a_in;
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aa <= (a_in(31) and sign_ext) & a_in;
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bb <= (b_in(31) and sign_ext) & b_in;
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bb <= (b_in(31) and sign_ext) & b_in;
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-- synthesis translate_off
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-- synthesis translate_off
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GENERIC_ALU: if alu_type="GENERIC" generate
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GENERIC_ALU: if alu_type="GENERIC" generate
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-- synthesis translate_on
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-- synthesis translate_on
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c_alu <= sum(31 downto 0) when alu_function=alu_add or alu_function=alu_subtract else
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c_alu <= sum(31 downto 0) when alu_function=ALU_ADD or alu_function=ALU_SUBTRACT else
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ZERO(31 downto 1) & sum(32) when alu_function=alu_less_than or alu_function=alu_less_than_signed else
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ZERO(31 downto 1) & sum(32) when alu_function=ALU_LESS_THAN or alu_function=ALU_LESS_THAN_SIGNED else
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a_in or b_in when alu_function=alu_or else
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a_in or b_in when alu_function=ALU_OR else
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a_in and b_in when alu_function=alu_and else
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a_in and b_in when alu_function=ALU_AND else
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a_in xor b_in when alu_function=alu_xor else
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a_in xor b_in when alu_function=ALU_XOR else
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a_in nor b_in when alu_function=alu_nor else
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a_in nor b_in when alu_function=ALU_NOR else
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ZERO;
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ZERO;
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-- synthesis translate_off
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-- synthesis translate_off
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end generate;
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end generate;
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-- synthesis translate_on
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-- synthesis translate_on
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-- synopsys synthesis_off
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-- synopsys synthesis_off
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AREA_OPTIMIZED_ALU: if alu_type="AREA_OPTIMIZED" generate
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AREA_OPTIMIZED_ALU: if alu_type="AREA_OPTIMIZED" generate
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c_alu <= sum(31 downto 0) when alu_function=alu_add or alu_function=alu_subtract else (others => 'Z');
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c_alu <= sum(31 downto 0) when alu_function=ALU_ADD or alu_function=ALU_SUBTRACT else (others => 'Z');
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c_alu <= ZERO(31 downto 1) & sum(32) when alu_function=alu_less_than or alu_function=alu_less_than_signed else (others => 'Z');
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c_alu <= ZERO(31 downto 1) & sum(32) when alu_function=ALU_LESS_THAN or alu_function=ALU_LESS_THAN_SIGNED else (others => 'Z');
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c_alu <= a_in or b_in when alu_function=alu_or else (others => 'Z');
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c_alu <= a_in or b_in when alu_function=ALU_OR else (others => 'Z');
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c_alu <= a_in and b_in when alu_function=alu_and else (others => 'Z');
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c_alu <= a_in and b_in when alu_function=ALU_AND else (others => 'Z');
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c_alu <= a_in xor b_in when alu_function=alu_xor else (others => 'Z');
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c_alu <= a_in xor b_in when alu_function=ALU_XOR else (others => 'Z');
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c_alu <= a_in nor b_in when alu_function=alu_nor else (others => 'Z');
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c_alu <= a_in nor b_in when alu_function=ALU_NOR else (others => 'Z');
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c_alu <= ZERO when alu_function=alu_nothing else (others => 'Z');
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c_alu <= ZERO when alu_function=ALU_NOTHING else (others => 'Z');
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end generate;
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end generate;
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generic_adder: if adder_type = "GENERIC" generate
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generic_adder: if adder_type = "GENERIC" generate
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sum <= bv_adder(aa, bb, do_add);
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sum <= bv_adder(aa, bb, do_add);
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