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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity alu is
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entity alu is
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generic(adder_type : string := "GENERIC");
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port(a_in : in std_logic_vector(31 downto 0);
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port(a_in : in std_logic_vector(31 downto 0);
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b_in : in std_logic_vector(31 downto 0);
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b_in : in std_logic_vector(31 downto 0);
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alu_function : in alu_function_type;
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alu_function : in alu_function_type;
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c_alu : out std_logic_vector(31 downto 0));
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c_alu : out std_logic_vector(31 downto 0));
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end; --alu
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end; --alu
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architecture logic of alu is
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architecture logic of alu is
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-- type alu_function_type is (alu_nothing, alu_add, alu_subtract,
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-- type alu_function_type is (alu_nothing, alu_add, alu_subtract,
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-- alu_less_than, alu_less_than_signed, alu_equal, alu_not_equal,
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-- alu_less_than, alu_less_than_signed, alu_equal, alu_not_equal,
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-- alu_ltz, alu_lez, alu_eqz, alu_nez, alu_gez, alu_gtz,
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-- alu_ltz, alu_lez, alu_eqz, alu_nez, alu_gez, alu_gtz,
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-- alu_or, alu_and, alu_xor, alu_nor);
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-- alu_or, alu_and, alu_xor, alu_nor);
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signal aa, bb, sum : std_logic_vector(32 downto 0);
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signal do_add : std_logic;
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begin
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begin
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alu_proc: process(a_in, b_in, alu_function)
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alu_proc: process(a_in, b_in, alu_function, sum)
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variable c : std_logic_vector(31 downto 0);
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variable c : std_logic_vector(31 downto 0);
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variable aa, bb, sum : std_logic_vector(32 downto 0);
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variable do_sub : std_logic;
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variable a_eq_b : std_logic;
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variable a_eq_b : std_logic;
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variable a_zero : std_logic;
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variable a_zero : std_logic;
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variable sign_ext : std_logic;
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variable sign_ext : std_logic;
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begin
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begin
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c := ZERO;
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c := ZERO;
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if alu_function = alu_add then
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if alu_function = alu_add then
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do_sub := '0';
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do_add <= '1';
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else
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else
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do_sub := '1';
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do_add <= '0';
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end if;
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end if;
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if alu_function = alu_less_than then
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if alu_function = alu_less_than then
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sign_ext := '0';
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sign_ext := '0';
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else
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else
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sign_ext := '1';
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sign_ext := '1';
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end if;
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end if;
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aa := (a_in(31) and sign_ext) & a_in;
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aa <= (a_in(31) and sign_ext) & a_in;
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bb := (b_in(31) and sign_ext) & b_in;
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bb <= (b_in(31) and sign_ext) & b_in;
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sum := bv_adder(aa, bb, do_sub);
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-- sum := bv_adder_lookahead(aa, bb, do_sub);
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-- Choose bv_adder or lpm_add_sub
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-- sum <= bv_adder(aa, bb, do_add);
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-- sum <= bv_adder_lookahead(aa, bb, do_add);
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if a_in = b_in then
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if a_in = b_in then
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a_eq_b := '1';
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a_eq_b := '1';
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else
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else
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a_eq_b := '0';
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a_eq_b := '0';
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end if;
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end if;
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end case;
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end case;
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c_alu <= c;
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c_alu <= c;
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end process;
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end process;
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generic_adder:
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if adder_type /= "ALTERA" generate
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sum <= bv_adder(aa, bb, do_add);
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end generate; --generic_adder
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--For Altera
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lpm_adder:
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if adder_type = "ALTERA" generate
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lpm_add_sub_component : lpm_add_sub
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GENERIC MAP (
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lpm_width => 33,
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lpm_direction => "UNUSED",
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lpm_type => "LPM_ADD_SUB",
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lpm_hint => "ONE_INPUT_IS_CONSTANT=NO"
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)
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PORT MAP (
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dataa => aa,
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add_sub => do_add,
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datab => bb,
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result => sum
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);
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end generate; --lpm_adder
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end; --architecture logic
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end; --architecture logic
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