| Line 29... |
Line 29... |
b_mux : in b_source_type;
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b_mux : in b_source_type;
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b_out : out std_logic_vector(31 downto 0);
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b_out : out std_logic_vector(31 downto 0);
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c_bus : in std_logic_vector(31 downto 0);
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c_bus : in std_logic_vector(31 downto 0);
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c_memory : in std_logic_vector(31 downto 0);
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c_memory : in std_logic_vector(31 downto 0);
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c_pc : in std_logic_vector(31 downto 0);
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c_pc : in std_logic_vector(31 downto 2);
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c_pc_plus4 : in std_logic_vector(31 downto 0);
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c_pc_plus4 : in std_logic_vector(31 downto 2);
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c_mux : in c_source_type;
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c_mux : in c_source_type;
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reg_dest_out : out std_logic_vector(31 downto 0);
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reg_dest_out : out std_logic_vector(31 downto 0);
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branch_func : in branch_function_type;
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branch_func : in branch_function_type;
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take_branch : out std_logic);
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take_branch : out std_logic);
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end; --entity bus_mux
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end; --entity bus_mux
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architecture logic of bus_mux is
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architecture logic of bus_mux is
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begin
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begin
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--Determine value of a_bus
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amux: process(reg_source, imm_in, a_mux, c_pc)
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amux: process(reg_source, imm_in, a_mux, c_pc)
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begin
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begin
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case a_mux is
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case a_mux is
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when A_FROM_REG_SOURCE =>
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when A_FROM_REG_SOURCE =>
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a_out <= reg_source;
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a_out <= reg_source;
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when A_FROM_IMM10_6 =>
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when A_FROM_IMM10_6 =>
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a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
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a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
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when A_FROM_PC =>
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when A_FROM_PC =>
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a_out <= c_pc;
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a_out <= c_pc & "00";
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when others =>
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when others =>
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a_out <= c_pc;
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a_out <= c_pc & "00";
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end case;
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end case;
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end process;
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end process;
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--Determine value of b_bus
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bmux: process(reg_target, imm_in, b_mux)
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bmux: process(reg_target, imm_in, b_mux)
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begin
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begin
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case b_mux is
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case b_mux is
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when B_FROM_REG_TARGET =>
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when B_FROM_REG_TARGET =>
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b_out <= reg_target;
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b_out <= reg_target;
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| Line 81... |
Line 83... |
when others =>
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when others =>
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b_out <= reg_target;
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b_out <= reg_target;
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end case;
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end case;
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end process;
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end process;
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--Determine value of c_bus
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cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
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cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
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begin
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begin
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case c_mux is
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case c_mux is
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when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
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when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
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reg_dest_out <= c_bus;
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reg_dest_out <= c_bus;
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when C_FROM_MEMORY =>
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when C_FROM_MEMORY =>
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reg_dest_out <= c_memory;
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reg_dest_out <= c_memory;
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when C_FROM_PC =>
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when C_FROM_PC =>
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reg_dest_out <= c_pc(31 downto 3) & "000"; --backup one opcode
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reg_dest_out <= c_pc(31 downto 2) & "00";
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when C_FROM_PC_PLUS4 =>
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when C_FROM_PC_PLUS4 =>
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reg_dest_out <= c_pc_plus4;
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reg_dest_out <= c_pc_plus4 & "00";
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when C_FROM_IMM_SHIFT16 =>
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when C_FROM_IMM_SHIFT16 =>
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reg_dest_out <= imm_in & ZERO(15 downto 0);
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reg_dest_out <= imm_in & ZERO(15 downto 0);
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when others =>
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when others =>
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reg_dest_out <= c_bus;
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reg_dest_out <= c_bus;
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end case;
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end case;
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end process;
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end process;
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--Determine value of take_branch
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pc_mux: process(branch_func, reg_source, reg_target)
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pc_mux: process(branch_func, reg_source, reg_target)
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variable is_equal : std_logic;
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variable is_equal : std_logic;
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begin
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begin
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if reg_source = reg_target then
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if reg_source = reg_target then
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is_equal := '1';
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is_equal := '1';
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| Line 123... |
Line 127... |
when BRANCH_GTZ =>
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when BRANCH_GTZ =>
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take_branch <= not reg_source(31) and not is_equal;
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take_branch <= not reg_source(31) and not is_equal;
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when BRANCH_YES =>
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when BRANCH_YES =>
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take_branch <= '1';
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take_branch <= '1';
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when others =>
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when others =>
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take_branch <= is_equal;
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take_branch <= '0';
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end case;
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end case;
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end process;
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end process;
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end; --architecture logic
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end; --architecture logic
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No newline at end of file
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No newline at end of file
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