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[/] [mlite/] [trunk/] [vhdl/] [bus_mux.vhd] - Diff between revs 7 and 39

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Line 1... Line 1...
---------------------------------------------------------------------
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- FILENAME: bus_mux.vhd
-- PROJECT: MIPS CPU core
-- PROJECT: M-lite CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- COPYRIGHT: Software placed into the public domain by the author.
--    Software 'as is' without warranty.  Author liable for nothing.
--    Software 'as is' without warranty.  Author liable for nothing.
-- DESCRIPTION:
-- DESCRIPTION:
--    This entity is the main signal router.  
--    This entity is the main signal router.  
--    It multiplexes signals from multiple sources to the correct location.
--    It multiplexes signals from multiple sources to the correct location.
Line 15... Line 15...
--       reg_dest_out : goes to the register bank
--       reg_dest_out : goes to the register bank
--       take_branch  : a signal to pc_next
--       take_branch  : a signal to pc_next
---------------------------------------------------------------------
---------------------------------------------------------------------
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use work.mips_pack.all;
use work.mlite_pack.all;
 
 
entity bus_mux is
entity bus_mux is
   port(imm_in       : in  std_logic_vector(15 downto 0);
   port(imm_in       : in  std_logic_vector(15 downto 0);
        reg_source   : in  std_logic_vector(31 downto 0);
        reg_source   : in  std_logic_vector(31 downto 0);
        a_mux        : in  a_source_type;
        a_mux        : in  a_source_type;

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