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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Bus Multiplexer / Signal Router
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-- TITLE: Bus Multiplexer / Signal Router
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 2/8/01
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-- DATE CREATED: 2/8/01
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-- FILENAME: bus_mux.vhd
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-- FILENAME: bus_mux.vhd
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-- PROJECT: MIPS CPU core
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-- PROJECT: M-lite CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- This entity is the main signal router.
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-- This entity is the main signal router.
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-- It multiplexes signals from multiple sources to the correct location.
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-- It multiplexes signals from multiple sources to the correct location.
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-- reg_dest_out : goes to the register bank
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-- reg_dest_out : goes to the register bank
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-- take_branch : a signal to pc_next
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-- take_branch : a signal to pc_next
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mips_pack.all;
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use work.mlite_pack.all;
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entity bus_mux is
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entity bus_mux is
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port(imm_in : in std_logic_vector(15 downto 0);
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port(imm_in : in std_logic_vector(15 downto 0);
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reg_source : in std_logic_vector(31 downto 0);
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reg_source : in std_logic_vector(31 downto 0);
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a_mux : in a_source_type;
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a_mux : in a_source_type;
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