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[/] [mlite/] [trunk/] [vhdl/] [ddr_ctrl.vhd] - Diff between revs 259 and 278
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| Rev 259 |
Rev 278 |
| Line 141... |
Line 141... |
end if;
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end if;
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end if;
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end if;
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when STATE_IDLE =>
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when STATE_IDLE =>
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if refresh_cnt(7) = '1' then
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if refresh_cnt(7) = '1' then
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if write_prev = '0' then
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state_current := STATE_PRECHARGE;
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state_current := STATE_PRECHARGE;
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command := COMMAND_AUTO_REFRESH;
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command := COMMAND_AUTO_REFRESH;
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end if;
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elsif active = '1' then
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elsif active = '1' then
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state_current := STATE_ROW_ACTIVATE;
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state_current := STATE_ROW_ACTIVATE;
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command := COMMAND_ACTIVE;
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command := COMMAND_ACTIVE;
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end if;
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end if;
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| Line 223... |
Line 221... |
write_active <= '1';
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write_active <= '1';
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elsif cycle_count2 = "100" then
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elsif cycle_count2 = "100" then
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write_active <= '0';
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write_active <= '0';
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end if;
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end if;
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if state_current = STATE_ROW_ACTIVATE then
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if command = COMMAND_ACTIVE then
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bank_open(bank_index) <= '1';
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bank_open(bank_index) <= '1';
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address_row(bank_index) := address(25 downto 13);
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address_row(bank_index) := address(25 downto 13);
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end if;
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end if;
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if state_current = COMMAND_AUTO_REFRESH then
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if command = COMMAND_PRECHARGE then
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bank_open <= "0000";
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bank_open <= "0000";
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end if;
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if command = COMMAND_AUTO_REFRESH then
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refresh_cnt <= ZERO(7 downto 0);
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refresh_cnt <= ZERO(7 downto 0);
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else
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else
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refresh_cnt <= refresh_cnt + 1;
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refresh_cnt <= refresh_cnt + 1;
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end if;
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end if;
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