| Line 50... |
Line 50... |
address : in std_logic_vector(25 downto 2);
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address : in std_logic_vector(25 downto 2);
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byte_we : in std_logic_vector(3 downto 0);
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byte_we : in std_logic_vector(3 downto 0);
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data_w : in std_logic_vector(31 downto 0);
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data_w : in std_logic_vector(31 downto 0);
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data_r : out std_logic_vector(31 downto 0);
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data_r : out std_logic_vector(31 downto 0);
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active : in std_logic;
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active : in std_logic;
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no_start : in std_logic;
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no_stop : in std_logic;
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pause : out std_logic;
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pause : out std_logic;
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SD_CK_P : out std_logic; --clock_positive
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SD_CK_P : out std_logic; --clock_positive
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SD_CK_N : out std_logic; --clock_negative
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SD_CK_N : out std_logic; --clock_negative
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SD_CKE : out std_logic; --clock_enable
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SD_CKE : out std_logic; --clock_enable
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| Line 109... |
Line 111... |
signal bank_open : std_logic_vector(3 downto 0);
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signal bank_open : std_logic_vector(3 downto 0);
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signal data_read : std_logic_vector(31 downto 0);
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signal data_read : std_logic_vector(31 downto 0);
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begin
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begin
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ddr_proc: process(clk, clk_p, clk_2x, reset_in,
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ddr_proc: process(clk, clk_p, clk_2x, reset_in,
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address, byte_we, data_w, active,
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address, byte_we, data_w, active, no_start, no_stop,
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SD_DQ, SD_UDQS, SD_LDQS,
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SD_DQ, SD_UDQS, SD_LDQS,
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state_prev, refresh_cnt,
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state_prev, refresh_cnt,
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byte_we_reg2, data_write2,
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byte_we_reg2, data_write2,
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cycle_count, cycle_count2, write_prev,
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cycle_count, cycle_count2, write_prev,
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write_active, cke_reg, bank_open,
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write_active, cke_reg, bank_open,
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| Line 143... |
Line 145... |
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when STATE_IDLE =>
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when STATE_IDLE =>
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if refresh_cnt(7) = '1' then
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if refresh_cnt(7) = '1' then
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state_current := STATE_PRECHARGE;
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state_current := STATE_PRECHARGE;
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command := COMMAND_AUTO_REFRESH;
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command := COMMAND_AUTO_REFRESH;
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elsif active = '1' then
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elsif active = '1' and no_start = '0' then
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state_current := STATE_ROW_ACTIVATE;
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state_current := STATE_ROW_ACTIVATE;
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command := COMMAND_ACTIVE;
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command := COMMAND_ACTIVE;
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end if;
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end if;
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when STATE_ROW_ACTIVATE =>
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when STATE_ROW_ACTIVATE =>
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| Line 157... |
Line 159... |
if refresh_cnt(7) = '1' then
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if refresh_cnt(7) = '1' then
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if write_prev = '0' then
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if write_prev = '0' then
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state_current := STATE_PRECHARGE;
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state_current := STATE_PRECHARGE;
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command := COMMAND_PRECHARGE;
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command := COMMAND_PRECHARGE;
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end if;
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end if;
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elsif active = '1' then
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elsif active = '1' and no_start = '0' then
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if bank_open(bank_index) = '0' then
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if bank_open(bank_index) = '0' then
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state_current := STATE_ROW_ACTIVATE;
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state_current := STATE_ROW_ACTIVATE;
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command := COMMAND_ACTIVE;
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command := COMMAND_ACTIVE;
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elsif address(25 downto 13) /= address_row(bank_index) then
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elsif address(25 downto 13) /= address_row(bank_index) then
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if write_prev = '0' then
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if write_prev = '0' then
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| Line 183... |
Line 185... |
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when STATE_READ2 =>
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when STATE_READ2 =>
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state_current := STATE_READ3;
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state_current := STATE_READ3;
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when STATE_READ3 =>
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when STATE_READ3 =>
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if no_stop = '0' then
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state_current := STATE_ROW_ACTIVE;
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state_current := STATE_ROW_ACTIVE;
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end if;
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when STATE_PRECHARGE =>
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when STATE_PRECHARGE =>
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state_current := STATE_PRECHARGE2;
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state_current := STATE_PRECHARGE2;
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when STATE_PRECHARGE2 =>
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when STATE_PRECHARGE2 =>
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