| Line 66... |
Line 66... |
--than letting the VHDL compiler accurately predict the maximum
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--than letting the VHDL compiler accurately predict the maximum
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--clock speed.
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--clock speed.
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signal address_reg : std_logic_vector(31 downto 0);
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signal address_reg : std_logic_vector(31 downto 0);
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signal write_reg : std_logic;
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signal write_reg : std_logic;
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signal byte_sel_reg : std_logic_vector(3 downto 0);
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signal byte_sel_reg : std_logic_vector(3 downto 0);
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signal mem_state_next_sig : mem_state_type;
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signal opcode_next_sig : std_logic_vector(31 downto 0);
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signal write_next_sig : std_logic;
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signal byte_sel_next_sig : std_logic_vector(3 downto 0);
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begin
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begin
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GEN_REGS: process(clk, reset_in)
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begin
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if reset_in = '1' then
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mem_state_reg <= STATE_FETCH;
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opcode_reg <= ZERO;
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next_opcode_reg <= ZERO;
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elsif rising_edge(clk) then
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mem_state_reg <= mem_state_next_sig;
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opcode_reg <= opcode_next_sig;
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if mem_state_reg = STATE_FETCH then
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next_opcode_reg <= mem_data_r;
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end if;
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end if;
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end process;
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GEN_REGS2: process(clk, address_data, write_next_sig, byte_sel_next_sig)
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begin
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if rising_edge(clk) then
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if ACCURATE_TIMING then
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address_reg <= address_data;
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write_reg <= write_next_sig;
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byte_sel_reg <= byte_sel_next_sig;
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end if;
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end if;
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if not ACCURATE_TIMING then
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address_reg <= address_data;
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write_reg <= write_next_sig;
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byte_sel_reg <= byte_sel_next_sig;
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end if;
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end process;
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mem_proc: process(clk, reset_in, pause_in, nullify_op,
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mem_proc: process(clk, reset_in, pause_in, nullify_op,
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address_pc, address_data, mem_source, data_write,
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address_pc, address_data, mem_source, data_write,
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mem_data_r,
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mem_data_r,
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opcode_reg, next_opcode_reg, mem_state_reg,
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opcode_reg, next_opcode_reg, mem_state_reg,
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address_reg, write_reg, byte_sel_reg)
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address_reg, write_reg, byte_sel_reg)
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| Line 150... |
Line 185... |
when others =>
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when others =>
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byte_sel_next := "0001";
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byte_sel_next := "0001";
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end case;
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end case;
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when others =>
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when others =>
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end case;
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end case;
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byte_sel_next_sig <= byte_sel_next;
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write_next_sig <= write_next;
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opcode_next := opcode_reg;
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opcode_next := opcode_reg;
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case mem_state_reg is --State Machine
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case mem_state_reg is --State Machine
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when STATE_FETCH =>
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when STATE_FETCH =>
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address := address_pc;
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address := address_pc;
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| Line 206... |
Line 243... |
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if nullify_op = '1' and pause_in = '0' then
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if nullify_op = '1' and pause_in = '0' then
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opcode_next := ZERO; --NOP after beql
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opcode_next := ZERO; --NOP after beql
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end if;
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end if;
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mem_state_next_sig <= mem_state_next;
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opcode_next_sig <= opcode_next;
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if reset_in = '1' then
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if reset_in = '1' then
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mem_state_reg <= STATE_FETCH;
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opcode_reg <= ZERO;
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next_opcode_reg <= ZERO;
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write_line := '0';
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write_line := '0';
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elsif rising_edge(clk) then
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mem_state_reg <= mem_state_next;
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opcode_reg <= opcode_next;
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if mem_state_reg = STATE_FETCH then
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next_opcode_reg <= mem_data_r;
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end if;
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end if;
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if rising_edge(clk) then
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if ACCURATE_TIMING then
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address_reg <= address_data;
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write_reg <= write_next;
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byte_sel_reg <= byte_sel_next;
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end if;
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end if;
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if not ACCURATE_TIMING then
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address_reg <= address_data;
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write_reg <= write_next;
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byte_sel_reg <= byte_sel_next;
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end if;
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end if;
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opcode_out <= opcode_reg;
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opcode_out <= opcode_reg;
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data_read <= data;
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data_read <= data;
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pause_out <= pause;
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pause_out <= pause;
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