| Line 42... |
Line 42... |
mem_write : out std_logic);
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mem_write : out std_logic);
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end; --entity mem_ctrl
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end; --entity mem_ctrl
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architecture logic of mem_ctrl is
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architecture logic of mem_ctrl is
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--"00" = big_endian; "11" = little_endian
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--"00" = big_endian; "11" = little_endian
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constant little_endian : std_logic_vector(1 downto 0) := "00";
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constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00";
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signal opcode_reg : std_logic_vector(31 downto 0);
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signal opcode_reg : std_logic_vector(31 downto 0);
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signal next_opcode_reg : std_logic_vector(31 downto 0);
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signal next_opcode_reg : std_logic_vector(31 downto 0);
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subtype mem_state_type is std_logic_vector(1 downto 0);
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subtype mem_state_type is std_logic_vector(1 downto 0);
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signal mem_state_reg : mem_state_type;
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signal mem_state_reg : mem_state_type;
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| Line 90... |
Line 90... |
end if;
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end if;
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end process;
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end process;
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GEN_REGS2: process(clk, address_data, write_next_sig, byte_sel_next_sig)
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GEN_REGS2: process(clk, address_data, write_next_sig, byte_sel_next_sig)
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begin
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begin
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if rising_edge(clk) then
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if reset_in = '1' then
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if ACCURATE_TIMING then
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address_reg <= ZERO;
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write_reg <= '0';
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byte_sel_reg <= "0000";
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end if;
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elsif rising_edge(clk) then
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if ACCURATE_TIMING then
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if ACCURATE_TIMING then
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address_reg <= address_data;
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address_reg <= address_data;
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write_reg <= write_next_sig;
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write_reg <= write_next_sig;
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byte_sel_reg <= byte_sel_next_sig;
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byte_sel_reg <= byte_sel_next_sig;
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end if;
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end if;
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| Line 130... |
Line 136... |
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data := ZERO;
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data := ZERO;
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mem_data_w_v := ZERO;
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mem_data_w_v := ZERO;
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case mem_source is
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case mem_source is
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when mem_read32 =>
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when MEM_READ32 =>
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data := mem_data_r;
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data := mem_data_r;
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when mem_read16 | mem_read16s =>
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if address_reg(1) = little_endian(1) then
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when MEM_READ16 | MEM_READ16S =>
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if address_reg(1) = ENDIAN_MODE(1) then
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data(15 downto 0) := mem_data_r(31 downto 16);
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data(15 downto 0) := mem_data_r(31 downto 16);
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else
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else
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data(15 downto 0) := mem_data_r(15 downto 0);
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data(15 downto 0) := mem_data_r(15 downto 0);
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end if;
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end if;
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if mem_source = mem_read16 or data(15) = '0' then
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if mem_source = mem_read16 or data(15) = '0' then
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data(31 downto 16) := ZERO(31 downto 16);
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data(31 downto 16) := ZERO(31 downto 16);
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else
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else
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data(31 downto 16) := ONES(31 downto 16);
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data(31 downto 16) := ONES(31 downto 16);
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end if;
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end if;
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when mem_read8 | mem_read8s =>
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bits := address_reg(1 downto 0) xor little_endian;
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when MEM_READ8 | MEM_READ8s =>
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bits := address_reg(1 downto 0) xor ENDIAN_MODE;
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case bits is
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case bits is
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when "00" => data(7 downto 0) := mem_data_r(31 downto 24);
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when "00" => data(7 downto 0) := mem_data_r(31 downto 24);
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when "01" => data(7 downto 0) := mem_data_r(23 downto 16);
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when "01" => data(7 downto 0) := mem_data_r(23 downto 16);
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when "10" => data(7 downto 0) := mem_data_r(15 downto 8);
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when "10" => data(7 downto 0) := mem_data_r(15 downto 8);
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when others => data(7 downto 0) := mem_data_r(7 downto 0);
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when others => data(7 downto 0) := mem_data_r(7 downto 0);
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end case;
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end case;
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if mem_source = mem_read8 or data(7) = '0' then
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if mem_source = MEM_READ8 or data(7) = '0' then
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data(31 downto 8) := ZERO(31 downto 8);
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data(31 downto 8) := ZERO(31 downto 8);
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else
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else
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data(31 downto 8) := ONES(31 downto 8);
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data(31 downto 8) := ONES(31 downto 8);
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end if;
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end if;
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when mem_write32 =>
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|
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when MEM_WRITE32 =>
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write_next := '1';
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write_next := '1';
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mem_data_w_v := data_write;
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mem_data_w_v := data_write;
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byte_sel_next := "1111";
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byte_sel_next := "1111";
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when mem_write16 =>
|
|
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when MEM_WRITE16 =>
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write_next := '1';
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write_next := '1';
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mem_data_w_v := data_write(15 downto 0) & data_write(15 downto 0);
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mem_data_w_v := data_write(15 downto 0) & data_write(15 downto 0);
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if address_data(1) = little_endian(1) then
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if address_data(1) = ENDIAN_MODE(1) then
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byte_sel_next := "1100";
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byte_sel_next := "1100";
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else
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else
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byte_sel_next := "0011";
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byte_sel_next := "0011";
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end if;
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end if;
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when mem_write8 =>
|
|
|
when MEM_WRITE8 =>
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write_next := '1';
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write_next := '1';
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mem_data_w_v := data_write(7 downto 0) & data_write(7 downto 0) &
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mem_data_w_v := data_write(7 downto 0) & data_write(7 downto 0) &
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data_write(7 downto 0) & data_write(7 downto 0);
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data_write(7 downto 0) & data_write(7 downto 0);
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bits := address_data(1 downto 0) xor little_endian;
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bits := address_data(1 downto 0) xor ENDIAN_MODE;
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case bits is
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case bits is
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when "00" =>
|
when "00" =>
|
byte_sel_next := "1000";
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byte_sel_next := "1000";
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when "01" =>
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when "01" =>
|
byte_sel_next := "0100";
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byte_sel_next := "0100";
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when "10" =>
|
when "10" =>
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byte_sel_next := "0010";
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byte_sel_next := "0010";
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when others =>
|
when others =>
|
byte_sel_next := "0001";
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byte_sel_next := "0001";
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end case;
|
end case;
|
|
|
when others =>
|
when others =>
|
end case;
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end case;
|
|
|
byte_sel_next_sig <= byte_sel_next;
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byte_sel_next_sig <= byte_sel_next;
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write_next_sig <= write_next;
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write_next_sig <= write_next;
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|
|
opcode_next := opcode_reg;
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opcode_next := opcode_reg;
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case mem_state_reg is --State Machine
|
case mem_state_reg is --State Machine
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| Line 205... |
Line 218... |
pause := '1';
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pause := '1';
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if pause_in = '0' then
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if pause_in = '0' then
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mem_state_next := STATE_ADDR;
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mem_state_next := STATE_ADDR;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when STATE_ADDR => --address lines pre-hold
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when STATE_ADDR => --address lines pre-hold
|
address := address_reg;
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address := address_reg;
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write_line := write_reg;
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write_line := write_reg;
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if write_reg = '1' and address_reg(31) = '1' then
|
if write_reg = '1' and address_reg(31) = '1' then
|
pause := '1';
|
pause := '1';
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| Line 221... |
Line 235... |
if pause_in = '0' then
|
if pause_in = '0' then
|
opcode_next := next_opcode_reg;
|
opcode_next := next_opcode_reg;
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mem_state_next := STATE_FETCH; --2 cycle access
|
mem_state_next := STATE_FETCH; --2 cycle access
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when STATE_WRITE =>
|
when STATE_WRITE =>
|
pause := '1';
|
pause := '1';
|
address := address_reg;
|
address := address_reg;
|
write_line := write_reg;
|
write_line := write_reg;
|
byte_sel := byte_sel_reg;
|
byte_sel := byte_sel_reg;
|
if pause_in = '0' then
|
if pause_in = '0' then
|
mem_state_next := STATE_PAUSE;
|
mem_state_next := STATE_PAUSE;
|
end if;
|
end if;
|
|
|
when OTHERS => --STATE_PAUSE address lines post-hold
|
when OTHERS => --STATE_PAUSE address lines post-hold
|
address := address_reg;
|
address := address_reg;
|
write_line := write_reg;
|
write_line := write_reg;
|
byte_sel := "0000";
|
byte_sel := "0000";
|
if pause_in = '0' then
|
if pause_in = '0' then
|
