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[/] [mlite/] [trunk/] [vhdl/] [mem_ctrl.vhd] - Diff between revs 128 and 129
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| Rev 128 |
Rev 129 |
| Line 88... |
Line 88... |
next_opcode_reg <= mem_data_r;
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next_opcode_reg <= mem_data_r;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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GEN_REGS2: process(clk, address_data, write_next_sig, byte_sel_next_sig)
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GEN_REGS2: process(clk, address_data, write_next_sig, byte_sel_next_sig, reset_in)
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begin
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begin
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if reset_in = '1' then
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if reset_in = '1' then
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if ACCURATE_TIMING then
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if ACCURATE_TIMING then
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address_reg <= ZERO;
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address_reg <= ZERO;
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write_reg <= '0';
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write_reg <= '0';
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