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[/] [mlite/] [trunk/] [vhdl/] [mem_ctrl.vhd] - Diff between revs 8 and 39
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Memory Controller
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-- TITLE: Memory Controller
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 1/31/01
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-- DATE CREATED: 1/31/01
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-- FILENAME: mem_ctrl.vhd
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-- FILENAME: mem_ctrl.vhd
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-- PROJECT: MIPS CPU core
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-- PROJECT: M-lite CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Memory controller for the MIPS CPU.
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-- Memory controller for the M-lite CPU.
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-- Supports Big or Little Endian mode.
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-- Supports Big or Little Endian mode.
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-- Four cycles for a write unless a(31)='1' then two cycles.
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-- Four cycles for a write unless a(31)='1' then two cycles.
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-- This entity could implement interfaces to:
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-- This entity could implement interfaces to:
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-- Data cache
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-- Data cache
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-- Address cache
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-- Address cache
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-- Memory management unit (MMU)
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-- Memory management unit (MMU)
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-- DRAM controller
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-- DRAM controller
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mips_pack.all;
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use work.mlite_pack.all;
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entity mem_ctrl is
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entity mem_ctrl is
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset_in : in std_logic;
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reset_in : in std_logic;
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pause_in : in std_logic;
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pause_in : in std_logic;
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