| Line 45... |
Line 45... |
architecture logic of mem_ctrl is
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architecture logic of mem_ctrl is
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--"00" = big_endian; "11" = little_endian
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--"00" = big_endian; "11" = little_endian
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constant little_endian : std_logic_vector(1 downto 0) := "00";
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constant little_endian : std_logic_vector(1 downto 0) := "00";
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signal opcode_reg : std_logic_vector(31 downto 0);
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signal opcode_reg : std_logic_vector(31 downto 0);
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signal next_opcode_reg : std_logic_vector(31 downto 0);
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signal next_opcode_reg : std_logic_vector(31 downto 0);
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signal mem_byte_sel_reg : std_logic_vector(3 downto 0);
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subtype mem_state_type is std_logic_vector(1 downto 0);
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subtype mem_state_type is std_logic_vector(1 downto 0);
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signal mem_state_reg : mem_state_type;
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signal mem_state_reg : mem_state_type;
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constant STATE_FETCH : mem_state_type := "00";
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constant STATE_FETCH : mem_state_type := "00";
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constant STATE_ADDR : mem_state_type := "01";
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constant STATE_ADDR : mem_state_type := "01";
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Line 58... |
begin
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begin
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mem_proc: process(clk, reset_in, pause_in, nullify_op,
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mem_proc: process(clk, reset_in, pause_in, nullify_op,
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address_pc, address_data, mem_source, data_write,
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address_pc, address_data, mem_source, data_write,
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mem_data_r, mem_pause,
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mem_data_r, mem_pause,
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opcode_reg, next_opcode_reg, mem_state_reg)
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opcode_reg, next_opcode_reg, mem_state_reg,
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mem_byte_sel_reg)
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variable data, datab : std_logic_vector(31 downto 0);
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variable data, datab : std_logic_vector(31 downto 0);
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variable opcode_next : std_logic_vector(31 downto 0);
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variable opcode_next : std_logic_vector(31 downto 0);
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variable byte_sel_next : std_logic_vector(3 downto 0);
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variable byte_sel_next : std_logic_vector(3 downto 0);
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variable write_next : std_logic;
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variable write_line : std_logic;
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variable mem_state_next : mem_state_type;
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variable mem_state_next : mem_state_type;
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variable pause : std_logic;
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variable pause : std_logic;
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variable address_next : std_logic_vector(31 downto 0);
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variable address_next : std_logic_vector(31 downto 0);
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variable bits : std_logic_vector(1 downto 0);
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variable bits : std_logic_vector(1 downto 0);
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variable mem_data_w_v : std_logic_vector(31 downto 0);
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variable mem_data_w_v : std_logic_vector(31 downto 0);
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begin
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begin
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byte_sel_next := "0000";
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byte_sel_next := "0000";
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write_next := '0';
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write_line := '0';
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pause := '0';
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pause := '0';
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mem_state_next := mem_state_reg;
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mem_state_next := mem_state_reg;
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address_next := address_pc;
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address_next := address_pc;
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data := mem_data_r;
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data := mem_data_r;
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Line 108... |
datab(31 downto 8) := ZERO(31 downto 8);
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datab(31 downto 8) := ZERO(31 downto 8);
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else
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else
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datab(31 downto 8) := ONES(31 downto 8);
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datab(31 downto 8) := ONES(31 downto 8);
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end if;
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end if;
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when mem_write32 =>
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when mem_write32 =>
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write_next := '1';
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write_line := '1';
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mem_data_w_v := data_write;
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mem_data_w_v := data_write;
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byte_sel_next := "1111";
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byte_sel_next := "1111";
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when mem_write16 =>
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when mem_write16 =>
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write_next := '1';
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write_line := '1';
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mem_data_w_v := data_write(15 downto 0) & data_write(15 downto 0);
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mem_data_w_v := data_write(15 downto 0) & data_write(15 downto 0);
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if address_data(1) = little_endian(1) then
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if address_data(1) = little_endian(1) then
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byte_sel_next := "1100";
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byte_sel_next := "1100";
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else
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else
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byte_sel_next := "0011";
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byte_sel_next := "0011";
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end if;
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end if;
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when mem_write8 =>
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when mem_write8 =>
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write_next := '1';
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write_line := '1';
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mem_data_w_v := data_write(7 downto 0) & data_write(7 downto 0) &
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mem_data_w_v := data_write(7 downto 0) & data_write(7 downto 0) &
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data_write(7 downto 0) & data_write(7 downto 0);
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data_write(7 downto 0) & data_write(7 downto 0);
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bits := address_data(1 downto 0) xor little_endian;
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bits := address_data(1 downto 0) xor little_endian;
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case bits is
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case bits is
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when "00" =>
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when "00" =>
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Line 138... |
end case;
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end case;
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when others =>
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when others =>
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end case;
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end case;
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opcode_next := opcode_reg;
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opcode_next := opcode_reg;
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if mem_source = mem_none then --opcode fetch
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if mem_source = mem_fetch then --opcode fetch
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mem_state_next := STATE_FETCH;
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mem_state_next := STATE_FETCH;
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if pause_in = '0' and mem_pause = '0' then
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if pause_in = '0' and mem_pause = '0' then
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opcode_next := data;
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opcode_next := data;
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end if;
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end if;
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else --data read or write (not opcode fetch)
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else --data read or write (not opcode fetch)
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case mem_state_reg is
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case mem_state_reg is
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when STATE_FETCH =>
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when STATE_FETCH =>
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write_line := '0';
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pause := '1';
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pause := '1';
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if address_data(31) = '0' then --4 cycle write
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byte_sel_next := "0000";
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byte_sel_next := "0000";
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end if;
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if mem_pause = '0' then
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if mem_pause = '0' then
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mem_state_next := STATE_ADDR;
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mem_state_next := STATE_ADDR;
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end if;
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end if;
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when STATE_ADDR => --address lines pre-hold
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when STATE_ADDR => --address lines pre-hold
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address_next := address_data;
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address_next := address_data;
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if write_next = '1' and address_data(31) = '0' then
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if write_line = '1' and address_data(31) = '0' then
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pause := '1';
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pause := '1';
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byte_sel_next := "0000";
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if mem_pause = '0' then
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if mem_pause = '0' then
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mem_state_next := STATE_WRITE; --4 cycle access
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mem_state_next := STATE_WRITE; --4 cycle access
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end if;
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end if;
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else
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else
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byte_sel_next := "0000";
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if mem_pause = '0' then
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if mem_pause = '0' then
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opcode_next := next_opcode_reg;
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opcode_next := next_opcode_reg;
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mem_state_next := STATE_FETCH; --2 cycle access
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mem_state_next := STATE_FETCH; --2 cycle access
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end if;
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end if;
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end if;
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end if;
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when STATE_WRITE =>
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when STATE_WRITE =>
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pause := '1';
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pause := '1';
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address_next := address_data;
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address_next := address_data;
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byte_sel_next := "0000";
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if mem_pause = '0' then
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if mem_pause = '0' then
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mem_state_next := STATE_PAUSE;
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mem_state_next := STATE_PAUSE;
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end if;
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end if;
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when OTHERS => --STATE_PAUSE address lines post-hold
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when OTHERS => --STATE_PAUSE address lines post-hold
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address_next := address_data;
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address_next := address_data;
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Line 188... |
end if;
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end if;
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if nullify_op = '1' then
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if nullify_op = '1' then
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opcode_next := ZERO; --NOP
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opcode_next := ZERO; --NOP
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end if;
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end if;
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if reset_in = '1' then
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mem_state_next := STATE_FETCH;
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opcode_next := ZERO;
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end if;
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if rising_edge(clk) then
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if reset_in = '1' then
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mem_state_reg <= STATE_FETCH;
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opcode_reg <= ZERO;
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next_opcode_reg <= ZERO;
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write_line := '0';
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mem_byte_sel_reg <= "0000";
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elsif rising_edge(clk) then
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mem_state_reg <= mem_state_next;
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opcode_reg <= opcode_next;
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opcode_reg <= opcode_next;
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if mem_state_reg = STATE_FETCH then
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if mem_state_reg = STATE_FETCH then
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next_opcode_reg <= data;
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next_opcode_reg <= data;
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end if;
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end if;
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mem_state_reg <= mem_state_next;
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mem_byte_sel_reg <= byte_sel_next;
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end if;
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end if;
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if reset_in = '0' then
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opcode_out <= opcode_reg;
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opcode_out <= opcode_reg;
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else
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opcode_out <= ZERO;
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end if;
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data_read <= datab;
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data_read <= datab;
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pause_out <= mem_pause or pause;
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pause_out <= mem_pause or pause;
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mem_byte_sel <= byte_sel_next;
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mem_byte_sel <= mem_byte_sel_reg;
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mem_address <= address_next;
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mem_address <= address_next;
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if write_next = '1' and mem_state_reg /= STATE_FETCH then
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mem_write <= write_line;
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mem_write <= '1';
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if write_line = '1' then
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mem_data_w <= mem_data_w_v;
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mem_data_w <= mem_data_w_v;
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else
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else
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mem_write <= '0';
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mem_data_w <= HIGH_Z; --ZERO;
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mem_data_w <= HIGH_Z; --ZERO;
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end if;
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end if;
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end process; --data_proc
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end process; --data_proc
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