| Line 47... |
Line 47... |
signal opcode_reg : std_logic_vector(31 downto 0);
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signal opcode_reg : std_logic_vector(31 downto 0);
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signal next_opcode_reg : std_logic_vector(31 downto 0);
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signal next_opcode_reg : std_logic_vector(31 downto 0);
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signal setup_done : std_logic;
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signal setup_done : std_logic;
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begin
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begin
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mem_proc: process(clk, reset_in, pause_in, nullify_op, address_pc,
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mem_proc: process(clk, reset_in, pause_in, nullify_op,
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address_data, mem_source, data_write, mem_data_r,
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address_pc, address_data, mem_source, data_write,
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mem_pause,
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mem_data_r, mem_pause,
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opcode_reg, next_opcode_reg, setup_done)
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opcode_reg, next_opcode_reg, setup_done)
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variable data, datab : std_logic_vector(31 downto 0);
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variable data, datab : std_logic_vector(31 downto 0);
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variable opcode_temp : std_logic_vector(31 downto 0);
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variable opcode_temp : std_logic_vector(31 downto 0);
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variable byte_sel_temp : std_logic_vector(3 downto 0);
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variable byte_sel_temp : std_logic_vector(3 downto 0);
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variable write_temp : std_logic;
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variable write_temp : std_logic;
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| Line 132... |
Line 132... |
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opcode_temp := opcode_reg;
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opcode_temp := opcode_reg;
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if mem_source = mem_none then
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if mem_source = mem_none then
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setup_done_var := '0';
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setup_done_var := '0';
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if pause_in = '0' and mem_pause = '0' then
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if pause_in = '0' and mem_pause = '0' then
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if nullify_op = '0' then
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opcode_temp := data;
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opcode_temp := data;
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else
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opcode_temp := ZERO; --NOP
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end if;
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end if;
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end if;
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else
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else
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pause := not setup_done;
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pause := not setup_done;
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setup_done_var := '1';
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setup_done_var := '1';
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if setup_done = '1' then
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if setup_done = '1' then
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Line 145... |
opcode_temp := next_opcode_reg;
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opcode_temp := next_opcode_reg;
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setup_done_var := '0';
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setup_done_var := '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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if nullify_op = '1' then
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opcode_temp := ZERO; --NOP
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end if;
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if reset_in = '1' then
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if reset_in = '1' then
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setup_done_var := '0';
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setup_done_var := '0';
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opcode_temp := ZERO;
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opcode_temp := ZERO;
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end if;
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end if;
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