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[/] [mlite/] [trunk/] [vhdl/] [mem_ctrl.vhd] - Diff between revs 56 and 72

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library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use work.mlite_pack.all;
 
 
entity mem_ctrl is
entity mem_ctrl is
 
   generic(ACCURATE_TIMING : boolean := false);
   port(clk          : in std_logic;
   port(clk          : in std_logic;
        reset_in     : in std_logic;
        reset_in     : in std_logic;
        pause_in     : in std_logic;
        pause_in     : in std_logic;
        nullify_op   : in std_logic;
        nullify_op   : in std_logic;
        address_pc   : in std_logic_vector(31 downto 0);
        address_pc   : in std_logic_vector(31 downto 0);
Line 36... Line 37...
 
 
        mem_address  : out std_logic_vector(31 downto 0);
        mem_address  : out std_logic_vector(31 downto 0);
        mem_data_w   : out std_logic_vector(31 downto 0);
        mem_data_w   : out std_logic_vector(31 downto 0);
        mem_data_r   : in std_logic_vector(31 downto 0);
        mem_data_r   : in std_logic_vector(31 downto 0);
        mem_byte_sel : out std_logic_vector(3 downto 0);
        mem_byte_sel : out std_logic_vector(3 downto 0);
        mem_write    : out std_logic;
        mem_write    : out std_logic);
        mem_pause    : in std_logic);
 
end; --entity mem_ctrl
end; --entity mem_ctrl
 
 
architecture logic of mem_ctrl is
architecture logic of mem_ctrl is
   --"00" = big_endian; "11" = little_endian
   --"00" = big_endian; "11" = little_endian
   constant little_endian  : std_logic_vector(1 downto 0) := "00";
   constant little_endian  : std_logic_vector(1 downto 0) := "00";
   signal opcode_reg       : std_logic_vector(31 downto 0);
   signal opcode_reg       : std_logic_vector(31 downto 0);
   signal next_opcode_reg  : std_logic_vector(31 downto 0);
   signal next_opcode_reg  : std_logic_vector(31 downto 0);
   signal mem_byte_sel_reg : std_logic_vector(3 downto 0);
   signal address_reg      : std_logic_vector(31 downto 0);
 
 
   subtype mem_state_type is std_logic_vector(1 downto 0);
   subtype mem_state_type is std_logic_vector(1 downto 0);
   signal mem_state_reg  : mem_state_type;
   signal mem_state_reg  : mem_state_type;
   constant STATE_FETCH  : mem_state_type := "00";
   constant STATE_FETCH  : mem_state_type := "00";
   constant STATE_ADDR   : mem_state_type := "01";
   constant STATE_ADDR   : mem_state_type := "01";
   constant STATE_WRITE  : mem_state_type := "10";
   constant STATE_WRITE  : mem_state_type := "10";
   constant STATE_PAUSE  : mem_state_type := "11";
   constant STATE_PAUSE  : mem_state_type := "11";
 
 
 
   --ACCURATE_TIMING notes:
 
   --The VHDL compiler's timing calculation isn't able to realize that
 
   --memory reads take two clock cycles.  It notices that reg_bank:reg_dest
 
   --is dependent on mem_ctrl:mem_data_r which is dependent on 
 
   --mem_ctrl:mem_address which is dependent on alu:c_alu.  However,
 
   --this dependency is only true for memory read or write cycles
 
   --which are multiple clock cycles.  Enabling ACCURATE_TIMING
 
   --creates an additional 32-bit register that does nothing other
 
   --than letting the VHDL compiler accurately predict the maximum
 
   --clock speed.
begin
begin
 
 
mem_proc: process(clk, reset_in, pause_in, nullify_op,
mem_proc: process(clk, reset_in, pause_in, nullify_op,
                  address_pc, address_data, mem_source, data_write,
                  address_pc, address_data, mem_source, data_write,
                  mem_data_r, mem_pause,
                  mem_data_r,
                  opcode_reg, next_opcode_reg, mem_state_reg,
                  opcode_reg, next_opcode_reg, mem_state_reg,
                  mem_byte_sel_reg)
                  address_reg)
   variable data, datab   : std_logic_vector(31 downto 0);
   variable data           : std_logic_vector(31 downto 0);
   variable opcode_next   : std_logic_vector(31 downto 0);
   variable opcode_next   : std_logic_vector(31 downto 0);
   variable byte_sel_next : std_logic_vector(3 downto 0);
   variable byte_sel       : std_logic_vector(3 downto 0);
   variable write_line    : std_logic;
   variable write_line    : std_logic;
   variable mem_state_next : mem_state_type;
   variable mem_state_next : mem_state_type;
   variable pause         : std_logic;
   variable pause         : std_logic;
   variable address_next  : std_logic_vector(31 downto 0);
   variable address        : std_logic_vector(31 downto 0);
   variable bits          : std_logic_vector(1 downto 0);
   variable bits          : std_logic_vector(1 downto 0);
   variable mem_data_w_v  : std_logic_vector(31 downto 0);
   variable mem_data_w_v  : std_logic_vector(31 downto 0);
begin
begin
   byte_sel_next := "0000";
   byte_sel := "0000";
   write_line := '0';
   write_line := '0';
   pause := '0';
   pause := '0';
   mem_state_next := mem_state_reg;
   mem_state_next := mem_state_reg;
 
 
   address_next := address_pc;
   address := address_pc;
   data := mem_data_r;
   data := ZERO;
   datab := ZERO;
 
   mem_data_w_v := ZERO;
   mem_data_w_v := ZERO;
 
 
   case mem_source is
   case mem_source is
   when mem_read32 =>
   when mem_read32 =>
      datab := data;
      data := mem_data_r;
   when mem_read16 | mem_read16s =>
   when mem_read16 | mem_read16s =>
      if address_data(1) = little_endian(1) then
      if address_reg(1) = little_endian(1) then
         datab(15 downto 0) := data(31 downto 16);
         data(15 downto 0) := mem_data_r(31 downto 16);
      else
      else
         datab(15 downto 0) := data(15 downto 0);
         data(15 downto 0) := mem_data_r(15 downto 0);
      end if;
      end if;
      if mem_source = mem_read16 or datab(15) = '0' then
      if mem_source = mem_read16 or data(15) = '0' then
         datab(31 downto 16) := ZERO(31 downto 16);
         data(31 downto 16) := ZERO(31 downto 16);
      else
      else
         datab(31 downto 16) := ONES(31 downto 16);
         data(31 downto 16) := ONES(31 downto 16);
      end if;
      end if;
   when mem_read8 | mem_read8s =>
   when mem_read8 | mem_read8s =>
      bits := address_data(1 downto 0) xor little_endian;
      bits := address_reg(1 downto 0) xor little_endian;
      case bits is
      case bits is
      when "00" => datab(7 downto 0) := data(31 downto 24);
      when "00" => data(7 downto 0) := mem_data_r(31 downto 24);
      when "01" => datab(7 downto 0) := data(23 downto 16);
      when "01" => data(7 downto 0) := mem_data_r(23 downto 16);
      when "10" => datab(7 downto 0) := data(15 downto 8);
      when "10" => data(7 downto 0) := mem_data_r(15 downto 8);
      when others => datab(7 downto 0) := data(7 downto 0);
      when others => data(7 downto 0) := mem_data_r(7 downto 0);
      end case;
      end case;
      if mem_source = mem_read8 or datab(7) = '0' then
      if mem_source = mem_read8 or data(7) = '0' then
         datab(31 downto 8) := ZERO(31 downto 8);
         data(31 downto 8) := ZERO(31 downto 8);
      else
      else
         datab(31 downto 8) := ONES(31 downto 8);
         data(31 downto 8) := ONES(31 downto 8);
      end if;
      end if;
   when mem_write32 =>
   when mem_write32 =>
      write_line := '1';
      write_line := '1';
      mem_data_w_v := data_write;
      mem_data_w_v := data_write;
      byte_sel_next := "1111";
      byte_sel := "1111";
   when mem_write16 =>
   when mem_write16 =>
      write_line := '1';
      write_line := '1';
      mem_data_w_v := data_write(15 downto 0) & data_write(15 downto 0);
      mem_data_w_v := data_write(15 downto 0) & data_write(15 downto 0);
      if address_data(1) = little_endian(1) then
      if address_data(1) = little_endian(1) then
         byte_sel_next := "1100";
         byte_sel := "1100";
      else
      else
         byte_sel_next := "0011";
         byte_sel := "0011";
      end if;
      end if;
   when mem_write8 =>
   when mem_write8 =>
      write_line := '1';
      write_line := '1';
      mem_data_w_v := data_write(7 downto 0) & data_write(7 downto 0) &
      mem_data_w_v := data_write(7 downto 0) & data_write(7 downto 0) &
                  data_write(7 downto 0) & data_write(7 downto 0);
                  data_write(7 downto 0) & data_write(7 downto 0);
      bits := address_data(1 downto 0) xor little_endian;
      bits := address_data(1 downto 0) xor little_endian;
      case bits is
      case bits is
      when "00" =>
      when "00" =>
         byte_sel_next := "1000";
         byte_sel := "1000";
      when "01" =>
      when "01" =>
         byte_sel_next := "0100";
         byte_sel := "0100";
      when "10" =>
      when "10" =>
         byte_sel_next := "0010";
         byte_sel := "0010";
      when others =>
      when others =>
         byte_sel_next := "0001";
         byte_sel := "0001";
      end case;
      end case;
   when others =>
   when others =>
   end case;
   end case;
 
 
   opcode_next := opcode_reg;
   opcode_next := opcode_reg;
   if mem_source = mem_fetch then --opcode fetch
   if mem_source = mem_fetch then --opcode fetch
      mem_state_next := STATE_FETCH;
      mem_state_next := STATE_FETCH;
      if pause_in = '0' and mem_pause = '0' then
      if pause_in = '0' then
         opcode_next := data;
         opcode_next := mem_data_r;
      end if;
      end if;
   else  --data read or write (not opcode fetch)
   else  --data read or write (not opcode fetch)
 
 
 
      --State Machine
      case mem_state_reg is
      case mem_state_reg is
      when STATE_FETCH =>
      when STATE_FETCH =>
         write_line := '0';
         write_line := '0';
         pause := '1';
         pause := '1';
         if address_data(31) = '0' then   --4 cycle write
         byte_sel := "0000";
            byte_sel_next := "0000";
         if pause_in = '0' then
         end if;
 
         if mem_pause = '0' then
 
            mem_state_next := STATE_ADDR;
            mem_state_next := STATE_ADDR;
         end if;
         end if;
      when STATE_ADDR =>  --address lines pre-hold
      when STATE_ADDR =>  --address lines pre-hold
         address_next := address_data;
         address := address_reg;
         if write_line = '1' and address_data(31) = '0' then
         if write_line = '1' and address_reg(31) = '1' then
            pause := '1';
            pause := '1';
            if mem_pause = '0' then
            byte_sel := "0000";
 
            if pause_in = '0' then
               mem_state_next := STATE_WRITE;    --4 cycle access
               mem_state_next := STATE_WRITE;    --4 cycle access
            end if;
            end if;
         else
         else
            byte_sel_next := "0000";
            if pause_in = '0' then
            if mem_pause = '0' then
 
               opcode_next := next_opcode_reg;
               opcode_next := next_opcode_reg;
               mem_state_next := STATE_FETCH;    --2 cycle access
               mem_state_next := STATE_FETCH;    --2 cycle access
            end if;
            end if;
         end if;
         end if;
      when STATE_WRITE =>
      when STATE_WRITE =>
         pause := '1';
         pause := '1';
         address_next := address_data;
         address := address_reg;
         byte_sel_next := "0000";
         if pause_in = '0' then
         if mem_pause = '0' then
 
            mem_state_next := STATE_PAUSE;
            mem_state_next := STATE_PAUSE;
         end if;
         end if;
      when OTHERS =>  --STATE_PAUSE address lines post-hold
      when OTHERS =>  --STATE_PAUSE address lines post-hold
         address_next := address_data;
         address := address_reg;
         byte_sel_next := "0000";
         byte_sel := "0000";
         if mem_pause = '0' then
         if pause_in = '0' then
            opcode_next := next_opcode_reg;
            opcode_next := next_opcode_reg;
            mem_state_next := STATE_FETCH;
            mem_state_next := STATE_FETCH;
         end if;
         end if;
      end case;
      end case;
   end if;
   end if;
Line 194... Line 203...
   if reset_in = '1' then
   if reset_in = '1' then
      mem_state_reg <= STATE_FETCH;
      mem_state_reg <= STATE_FETCH;
      opcode_reg <= ZERO;
      opcode_reg <= ZERO;
          next_opcode_reg <= ZERO;
          next_opcode_reg <= ZERO;
      write_line := '0';
      write_line := '0';
      mem_byte_sel_reg <= "0000";
 
   elsif rising_edge(clk) then
   elsif rising_edge(clk) then
      mem_state_reg <= mem_state_next;
      mem_state_reg <= mem_state_next;
      opcode_reg <= opcode_next;
      opcode_reg <= opcode_next;
      if mem_state_reg = STATE_FETCH then
      if mem_state_reg = STATE_FETCH then
         next_opcode_reg <= data;
         next_opcode_reg <= mem_data_r;
 
      end if;
 
   end if;
 
 
 
   if rising_edge(clk) then
 
      if ACCURATE_TIMING then
 
         address_reg <= address_data;
 
      end if;
      end if;
      end if;
      mem_byte_sel_reg <= byte_sel_next;
   if not ACCURATE_TIMING then
 
      address_reg <= address_data;
   end if;
   end if;
 
 
   opcode_out <= opcode_reg;
   opcode_out <= opcode_reg;
   data_read <= datab;
   data_read <= data;
   pause_out <= mem_pause or pause;
   pause_out <= pause;
   mem_byte_sel <= mem_byte_sel_reg;
   mem_byte_sel <= byte_sel;
   mem_address <= address_next;
   mem_address <= address;
   mem_write <= write_line;
   mem_write <= write_line;
 
 
   if write_line = '1' then
   if write_line = '1' then
      mem_data_w <= mem_data_w_v;
      mem_data_w <= mem_data_w_v;
   else
   else

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