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[/] [mlite/] [trunk/] [vhdl/] [mem_ctrl.vhd] - Diff between revs 72 and 89
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| Rev 72 |
Rev 89 |
| Line 124... |
Line 124... |
mem_data_w_v := data_write;
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mem_data_w_v := data_write;
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byte_sel := "1111";
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byte_sel := "1111";
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when mem_write16 =>
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when mem_write16 =>
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write_line := '1';
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write_line := '1';
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mem_data_w_v := data_write(15 downto 0) & data_write(15 downto 0);
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mem_data_w_v := data_write(15 downto 0) & data_write(15 downto 0);
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if address_data(1) = little_endian(1) then
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if address_reg(1) = little_endian(1) then
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byte_sel := "1100";
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byte_sel := "1100";
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else
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else
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byte_sel := "0011";
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byte_sel := "0011";
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end if;
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end if;
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when mem_write8 =>
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when mem_write8 =>
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write_line := '1';
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write_line := '1';
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mem_data_w_v := data_write(7 downto 0) & data_write(7 downto 0) &
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mem_data_w_v := data_write(7 downto 0) & data_write(7 downto 0) &
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data_write(7 downto 0) & data_write(7 downto 0);
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data_write(7 downto 0) & data_write(7 downto 0);
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bits := address_data(1 downto 0) xor little_endian;
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bits := address_reg(1 downto 0) xor little_endian;
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case bits is
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case bits is
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when "00" =>
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when "00" =>
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byte_sel := "1000";
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byte_sel := "1000";
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when "01" =>
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when "01" =>
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byte_sel := "0100";
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byte_sel := "0100";
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| Line 195... |
Line 195... |
end if;
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end if;
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end case;
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end case;
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end if;
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end if;
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if nullify_op = '1' then
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if nullify_op = '1' then
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opcode_next := ZERO; --NOP
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opcode_next := ZERO; --NOP after beql
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end if;
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end if;
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if reset_in = '1' then
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if reset_in = '1' then
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mem_state_reg <= STATE_FETCH;
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mem_state_reg <= STATE_FETCH;
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opcode_reg <= ZERO;
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opcode_reg <= ZERO;
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