URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] [mlite_cpu.vhd] - Diff between revs 114 and 120

Rev 114	Rev 120
Line 72...	Line 72...
`--use mlite_lib.mlite_pack.all;`	`--use mlite_lib.mlite_pack.all;`
`use ieee.std_logic_1164.all;`	`use ieee.std_logic_1164.all;`
`use ieee.std_logic_unsigned.all;`	`use ieee.std_logic_unsigned.all;`

`entity mlite_cpu is`	`entity mlite_cpu is`
`generic(memory_type : string := "DUAL_PORT_XILINX_XC4000XLA";`	`generic(memory_type : string := "GENERIC"; --DUAL_PORT_XILINX_XC4000XLA`
`adder_type : string := "GENERIC";`	`adder_type : string := "GENERIC"; --AREA_OPTIMIZED`
`mult_type : string := "AREA_OPTIMIZED";`	`mult_type : string := "GENERIC"; --AREA_OPTIMIZED`
`shifter_type : string := "GENERIC";`	`shifter_type : string := "GENERIC"; --AREA_OPTIMIZED`
`alu_type : string := "GENERIC";`	`alu_type : string := "GENERIC"; --AREA_OPTIMIZED`
`pipeline_stages : natural := 3;`	`pipeline_stages : natural := 3;`
`accurate_timing : boolean := true);`	`accurate_timing : boolean := true);`
`port(clk : in std_logic;`	`port(clk : in std_logic;`
`reset_in : in std_logic;`	`reset_in : in std_logic;`
`intr_in : in std_logic;`	`intr_in : in std_logic;`