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[/] [mlite/] [trunk/] [vhdl/] [mlite_cpu.vhd] - Diff between revs 139 and 194

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Rev 139 Rev 194
Line 135... Line 135...
   signal pause_non_ctrl : std_logic;
   signal pause_non_ctrl : std_logic;
   signal pause_bank     : std_logic;
   signal pause_bank     : std_logic;
   signal nullify_op     : std_logic;
   signal nullify_op     : std_logic;
   signal intr_enable    : std_logic;
   signal intr_enable    : std_logic;
   signal intr_signal    : std_logic;
   signal intr_signal    : std_logic;
 
   signal exception_sig  : std_logic;
   signal reset_reg      : std_logic_vector(3 downto 0);
   signal reset_reg      : std_logic_vector(3 downto 0);
   signal reset          : std_logic;
   signal reset          : std_logic;
begin  --architecture
begin  --architecture
 
 
   pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);
   pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);
   pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;
   pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;
   pause_bank <= (mem_pause or pause_ctrl or pause_mult) and not pause_pipeline;
   pause_bank <= (mem_pause or pause_ctrl or pause_mult) and not pause_pipeline;
   nullify_op <= '1' when (pc_source = FROM_LBRANCH and take_branch = '0')
   nullify_op <= '1' when (pc_source = FROM_LBRANCH and take_branch = '0')
                          or intr_signal = '1'
                          or intr_signal = '1' or exception_sig = '1'
                          else '0';
                          else '0';
   c_bus <= c_alu or c_shift or c_mult;
   c_bus <= c_alu or c_shift or c_mult;
   reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
   reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
   mem_address(1 downto 0) <= "00";
   mem_address(1 downto 0) <= "00";
 
 
Line 222... Line 223...
        branch_func  => branch_func,
        branch_func  => branch_func,
        a_source_out => a_source,
        a_source_out => a_source,
        b_source_out => b_source,
        b_source_out => b_source,
        c_source_out => c_source,
        c_source_out => c_source,
        pc_source_out=> pc_source,
        pc_source_out=> pc_source,
        mem_source_out=> mem_source);
        mem_source_out=> mem_source,
 
        exception_out=> exception_sig);
 
 
   u4_reg_bank: reg_bank
   u4_reg_bank: reg_bank
      generic map(memory_type => memory_type)
      generic map(memory_type => memory_type)
      port map (
      port map (
        clk            => clk,
        clk            => clk,

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