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-- TITLE: M-lite CPU core
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-- TITLE: Plasma CPU core
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 2/15/01
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-- DATE CREATED: 2/15/01
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-- FILENAME: mlite_cpu.vhd
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-- FILENAME: mlite_cpu.vhd
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-- PROJECT: M-lite CPU core
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- NOTE: MIPS(tm) and MIPS I(tm) are registered trademarks of MIPS
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-- NOTE: MIPS(tm) and MIPS I(tm) are registered trademarks of MIPS
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-- Technologies. MIPS Technologies does not endorse and is not
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-- Technologies. MIPS Technologies does not endorse and is not
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-- associated with this project.
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-- associated with this project.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Top level VHDL document that ties the eight other entities together.
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-- Top level VHDL document that ties the eight other entities together.
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-- Executes MIPS(tm) opcodes. Based on information found in:
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-- Executes most MIPS I(tm) opcodes. Based on information found in:
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-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
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-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
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-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
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-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
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-- An add instruction would take the following steps (see cpu.gif):
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-- An add instruction would take the following steps (see cpu.gif):
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-- 1. The "pc_next" entity would have previously passed the program
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-- 1. The "pc_next" entity would have previously passed the program
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-- counter (PC) to the "mem_ctrl" entity.
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-- counter (PC) to the "mem_ctrl" entity.
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