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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity mlite_cpu is
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entity mlite_cpu is
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generic(memory_type : string := "ALTERA");
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset_in : in std_logic;
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reset_in : in std_logic;
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intr_in : in std_logic;
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intr_in : in std_logic;
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mem_address : out std_logic_vector(31 downto 0);
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mem_address : out std_logic_vector(31 downto 0);
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mem_write : out std_logic;
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mem_write : out std_logic;
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mem_pause : in std_logic);
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mem_pause : in std_logic);
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end; --entity mlite_cpu
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end; --entity mlite_cpu
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architecture logic of mlite_cpu is
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architecture logic of mlite_cpu is
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component pc_next
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port(clk : in std_logic;
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reset_in : in std_logic;
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pc_new : in std_logic_vector(31 downto 2);
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take_branch : in std_logic;
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pause_in : in std_logic;
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opcode25_0 : in std_logic_vector(25 downto 0);
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pc_source : in pc_source_type;
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pc_out : out std_logic_vector(31 downto 0);
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pc_out_plus4 : out std_logic_vector(31 downto 0));
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end component;
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component mem_ctrl
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port(clk : in std_logic;
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reset_in : in std_logic;
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pause_in : in std_logic;
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nullify_op : in std_logic;
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address_pc : in std_logic_vector(31 downto 0);
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opcode_out : out std_logic_vector(31 downto 0);
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address_data : in std_logic_vector(31 downto 0);
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mem_source : in mem_source_type;
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data_write : in std_logic_vector(31 downto 0);
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data_read : out std_logic_vector(31 downto 0);
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pause_out : out std_logic;
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mem_address : out std_logic_vector(31 downto 0);
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mem_data_w : out std_logic_vector(31 downto 0);
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mem_data_r : in std_logic_vector(31 downto 0);
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mem_byte_sel : out std_logic_vector(3 downto 0);
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mem_write : out std_logic;
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mem_pause : in std_logic);
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end component;
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component control
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port(opcode : in std_logic_vector(31 downto 0);
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intr_signal : in std_logic;
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pause_in : in std_logic;
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rs_index : out std_logic_vector(5 downto 0);
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rt_index : out std_logic_vector(5 downto 0);
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rd_index : out std_logic_vector(5 downto 0);
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imm_out : out std_logic_vector(15 downto 0);
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alu_func : out alu_function_type;
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shift_func : out shift_function_type;
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mult_func : out mult_function_type;
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branch_func : out branch_function_type;
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a_source_out : out a_source_type;
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b_source_out : out b_source_type;
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c_source_out : out c_source_type;
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pc_source_out: out pc_source_type;
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mem_source_out:out mem_source_type);
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end component;
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component reg_bank
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port(clk : in std_logic;
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reset_in : in std_logic;
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rs_index : in std_logic_vector(5 downto 0);
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rt_index : in std_logic_vector(5 downto 0);
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rd_index : in std_logic_vector(5 downto 0);
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reg_source_out : out std_logic_vector(31 downto 0);
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reg_target_out : out std_logic_vector(31 downto 0);
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reg_dest_new : in std_logic_vector(31 downto 0);
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intr_enable : out std_logic);
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end component;
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component bus_mux
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port(imm_in : in std_logic_vector(15 downto 0);
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reg_source : in std_logic_vector(31 downto 0);
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a_mux : in a_source_type;
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a_out : out std_logic_vector(31 downto 0);
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reg_target : in std_logic_vector(31 downto 0);
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b_mux : in b_source_type;
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b_out : out std_logic_vector(31 downto 0);
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c_bus : in std_logic_vector(31 downto 0);
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c_memory : in std_logic_vector(31 downto 0);
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c_pc : in std_logic_vector(31 downto 0);
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c_pc_plus4 : in std_logic_vector(31 downto 0);
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c_mux : in c_source_type;
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reg_dest_out : out std_logic_vector(31 downto 0);
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branch_func : in branch_function_type;
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take_branch : out std_logic);
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end component;
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component alu
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port(a_in : in std_logic_vector(31 downto 0);
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b_in : in std_logic_vector(31 downto 0);
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alu_function : in alu_function_type;
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c_alu : out std_logic_vector(31 downto 0));
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end component;
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component shifter
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port(value : in std_logic_vector(31 downto 0);
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shift_amount : in std_logic_vector(4 downto 0);
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shift_func : in shift_function_type;
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c_shift : out std_logic_vector(31 downto 0));
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end component;
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component mult
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port(clk : in std_logic;
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a, b : in std_logic_vector(31 downto 0);
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mult_func : in mult_function_type;
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c_mult : out std_logic_vector(31 downto 0);
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pause_out : out std_logic);
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end component;
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signal opcode : std_logic_vector(31 downto 0);
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signal opcode : std_logic_vector(31 downto 0);
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signal rs_index, rt_index, rd_index : std_logic_vector(5 downto 0);
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signal rs_index, rt_index, rd_index : std_logic_vector(5 downto 0);
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signal reg_source, reg_target, reg_dest : std_logic_vector(31 downto 0);
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signal reg_source, reg_target, reg_dest : std_logic_vector(31 downto 0);
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signal a_bus, b_bus, c_bus : std_logic_vector(31 downto 0);
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signal a_bus, b_bus, c_bus : std_logic_vector(31 downto 0);
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signal c_alu, c_shift, c_mult, c_memory
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signal c_alu, c_shift, c_mult, c_memory
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Line 172... |
b_source_out => b_source,
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b_source_out => b_source,
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c_source_out => c_source,
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c_source_out => c_source,
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pc_source_out=> pc_source,
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pc_source_out=> pc_source,
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mem_source_out=> mem_source);
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mem_source_out=> mem_source);
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u4_reg_bank: reg_bank port map (
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u4_reg_bank: reg_bank
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generic map(memory_type => memory_type)
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port map (
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clk => clk,
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clk => clk,
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reset_in => reset_reg,
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reset_in => reset_reg,
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rs_index => rs_index,
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rs_index => rs_index,
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rt_index => rt_index,
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rt_index => rt_index,
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rd_index => rd_index,
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rd_index => rd_index,
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Line 205... |
reg_dest_out => reg_dest,
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reg_dest_out => reg_dest,
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branch_func => branch_function,
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branch_func => branch_function,
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take_branch => take_branch);
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take_branch => take_branch);
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u6_alu: alu port map (
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u6_alu: alu
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generic map (adder_type => memory_type)
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port map (
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a_in => a_bus,
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a_in => a_bus,
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b_in => b_bus,
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b_in => b_bus,
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alu_function => alu_function,
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alu_function => alu_function,
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c_alu => c_alu);
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c_alu => c_alu);
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Line 219... |
value => b_bus,
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value => b_bus,
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shift_amount => a_bus(4 downto 0),
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shift_amount => a_bus(4 downto 0),
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shift_func => shift_function,
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shift_func => shift_function,
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c_shift => c_shift);
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c_shift => c_shift);
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u8_mult: mult port map (
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u8_mult: mult
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generic map (adder_type => memory_type)
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port map (
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clk => clk,
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clk => clk,
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a => a_bus,
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a => a_bus,
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b => b_bus,
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b => b_bus,
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mult_func => mult_function,
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mult_func => mult_function,
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c_mult => c_mult,
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c_mult => c_mult,
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