| Line 204... |
Line 204... |
dib : in std_logic_vector;
|
dib : in std_logic_vector;
|
enb : in std_logic;
|
enb : in std_logic;
|
web : in std_logic);
|
web : in std_logic);
|
end component;
|
end component;
|
|
|
|
-- For Xilinx
|
|
component reg_file_dp_ram
|
|
port (
|
|
addra : IN std_logic_VECTOR(4 downto 0);
|
|
addrb : IN std_logic_VECTOR(4 downto 0);
|
|
clka : IN std_logic;
|
|
clkb : IN std_logic;
|
|
dinb : IN std_logic_VECTOR(31 downto 0);
|
|
douta : OUT std_logic_VECTOR(31 downto 0);
|
|
web : IN std_logic);
|
|
end component;
|
|
|
|
-- For Xilinx
|
|
component reg_file_dp_ram_xc4000xla
|
|
port (
|
|
A : IN std_logic_vector(4 DOWNTO 0);
|
|
DI : IN std_logic_vector(31 DOWNTO 0);
|
|
WR_EN : IN std_logic;
|
|
WR_CLK : IN std_logic;
|
|
DPRA : IN std_logic_vector(4 DOWNTO 0);
|
|
SPO : OUT std_logic_vector(31 DOWNTO 0);
|
|
DPO : OUT std_logic_vector(31 DOWNTO 0));
|
|
end component;
|
|
|
component pc_next
|
component pc_next
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
pc_new : in std_logic_vector(31 downto 2);
|
pc_new : in std_logic_vector(31 downto 2);
|
take_branch : in std_logic;
|
take_branch : in std_logic;
|
| Line 292... |
Line 316... |
branch_func : in branch_function_type;
|
branch_func : in branch_function_type;
|
take_branch : out std_logic);
|
take_branch : out std_logic);
|
end component;
|
end component;
|
|
|
component alu
|
component alu
|
generic(adder_type : string := "GENERIC");
|
generic(adder_type : string := "GENERIC";
|
|
alu_type : string := "GENERIC");
|
port(a_in : in std_logic_vector(31 downto 0);
|
port(a_in : in std_logic_vector(31 downto 0);
|
b_in : in std_logic_vector(31 downto 0);
|
b_in : in std_logic_vector(31 downto 0);
|
alu_function : in alu_function_type;
|
alu_function : in alu_function_type;
|
c_alu : out std_logic_vector(31 downto 0));
|
c_alu : out std_logic_vector(31 downto 0));
|
end component;
|
end component;
|
|
|
component shifter
|
component shifter
|
|
generic( shifter_type : string := "GENERIC" );
|
port(value : in std_logic_vector(31 downto 0);
|
port(value : in std_logic_vector(31 downto 0);
|
shift_amount : in std_logic_vector(4 downto 0);
|
shift_amount : in std_logic_vector(4 downto 0);
|
shift_func : in shift_function_type;
|
shift_func : in shift_function_type;
|
c_shift : out std_logic_vector(31 downto 0));
|
c_shift : out std_logic_vector(31 downto 0));
|
end component;
|
end component;
|
|
|
component mult
|
component mult
|
generic(adder_type : string := "GENERIC");
|
generic (
|
port(clk : in std_logic;
|
adder_type : string := "GENERIC";
|
|
mult_type : string := "GENERIC");
|
|
port (
|
|
clk : in std_logic;
|
a, b : in std_logic_vector(31 downto 0);
|
a, b : in std_logic_vector(31 downto 0);
|
mult_func : in mult_function_type;
|
mult_func : in mult_function_type;
|
c_mult : out std_logic_vector(31 downto 0);
|
c_mult : out std_logic_vector(31 downto 0);
|
pause_out : out std_logic);
|
pause_out : out std_logic);
|
end component;
|
end component;
|
| Line 347... |
Line 376... |
pause_pipeline : out std_logic);
|
pause_pipeline : out std_logic);
|
end component;
|
end component;
|
|
|
component mlite_cpu
|
component mlite_cpu
|
generic(memory_type : string := "ALTERA";
|
generic(memory_type : string := "ALTERA";
|
|
mult_type : string := "GENERIC";
|
|
shifter_type : string := "GENERIC";
|
pipeline_stages : natural := 3);
|
pipeline_stages : natural := 3);
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
intr_in : in std_logic;
|
intr_in : in std_logic;
|
|
|
