| Line 107... |
Line 107... |
) return std_logic_vector;
|
) return std_logic_vector;
|
function bv_inc(a : in std_logic_vector
|
function bv_inc(a : in std_logic_vector
|
) return std_logic_vector;
|
) return std_logic_vector;
|
|
|
-- For Altera
|
-- For Altera
|
COMPONENT lpm_add_sub
|
|
GENERIC (
|
|
lpm_width : NATURAL;
|
|
lpm_direction : STRING := "UNUSED";
|
|
lpm_type : STRING;
|
|
lpm_hint : STRING);
|
|
PORT (
|
|
dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
|
|
add_sub : IN STD_LOGIC ;
|
|
datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
|
|
result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0));
|
|
END COMPONENT;
|
|
|
|
-- For Altera
|
|
COMPONENT lpm_ram_dp
|
COMPONENT lpm_ram_dp
|
GENERIC (
|
GENERIC (
|
lpm_width : NATURAL;
|
lpm_width : NATURAL;
|
lpm_widthad : NATURAL;
|
lpm_widthad : NATURAL;
|
rden_used : STRING;
|
rden_used : STRING;
|
| Line 166... |
Line 152... |
WE : in std_logic;
|
WE : in std_logic;
|
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
|
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
|
end component;
|
end component;
|
|
|
-- For Xilinx
|
-- For Xilinx
|
component ramb4_s16_s16
|
component RAM16X1D
|
port (
|
-- synthesis translate_off
|
clka : in std_logic;
|
generic (INIT : bit_vector := X"16");
|
rsta : in std_logic;
|
-- synthesis translate_on
|
addra : in std_logic_vector;
|
port (DPO : out STD_ULOGIC;
|
dia : in std_logic_vector;
|
SPO : out STD_ULOGIC;
|
ena : in std_logic;
|
A0 : in STD_ULOGIC;
|
wea : in std_logic;
|
A1 : in STD_ULOGIC;
|
doa : out std_logic_vector;
|
A2 : in STD_ULOGIC;
|
|
A3 : in STD_ULOGIC;
|
clkb : in std_logic;
|
D : in STD_ULOGIC;
|
rstb : in std_logic;
|
DPRA0 : in STD_ULOGIC;
|
addrb : in std_logic_vector;
|
DPRA1 : in STD_ULOGIC;
|
dib : in std_logic_vector;
|
DPRA2 : in STD_ULOGIC;
|
enb : in std_logic;
|
DPRA3 : in STD_ULOGIC;
|
web : in std_logic);
|
WCLK : in STD_ULOGIC;
|
end component;
|
WE : in STD_ULOGIC);
|
|
|
-- For Xilinx
|
|
component reg_file_dp_ram
|
|
port (
|
|
addra : IN std_logic_VECTOR(4 downto 0);
|
|
addrb : IN std_logic_VECTOR(4 downto 0);
|
|
clka : IN std_logic;
|
|
clkb : IN std_logic;
|
|
dinb : IN std_logic_VECTOR(31 downto 0);
|
|
douta : OUT std_logic_VECTOR(31 downto 0);
|
|
web : IN std_logic);
|
|
end component;
|
|
|
|
-- For Xilinx
|
|
component reg_file_dp_ram_xc4000xla
|
|
port (
|
|
A : IN std_logic_vector(4 DOWNTO 0);
|
|
DI : IN std_logic_vector(31 DOWNTO 0);
|
|
WR_EN : IN std_logic;
|
|
WR_CLK : IN std_logic;
|
|
DPRA : IN std_logic_vector(4 DOWNTO 0);
|
|
SPO : OUT std_logic_vector(31 DOWNTO 0);
|
|
DPO : OUT std_logic_vector(31 DOWNTO 0));
|
|
end component;
|
end component;
|
|
|
component pc_next
|
component pc_next
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
| Line 235... |
Line 198... |
mem_source : in mem_source_type;
|
mem_source : in mem_source_type;
|
data_write : in std_logic_vector(31 downto 0);
|
data_write : in std_logic_vector(31 downto 0);
|
data_read : out std_logic_vector(31 downto 0);
|
data_read : out std_logic_vector(31 downto 0);
|
pause_out : out std_logic;
|
pause_out : out std_logic;
|
|
|
mem_address : out std_logic_vector(31 downto 2);
|
address_next : out std_logic_vector(31 downto 2);
|
mem_data_w : out std_logic_vector(31 downto 0);
|
byte_we_next : out std_logic_vector(3 downto 0);
|
mem_data_r : in std_logic_vector(31 downto 0);
|
|
mem_byte_we : out std_logic_vector(3 downto 0));
|
address : out std_logic_vector(31 downto 2);
|
|
byte_we : out std_logic_vector(3 downto 0);
|
|
data_w : out std_logic_vector(31 downto 0);
|
|
data_r : in std_logic_vector(31 downto 0));
|
end component;
|
end component;
|
|
|
component control
|
component control
|
port(opcode : in std_logic_vector(31 downto 0);
|
port(opcode : in std_logic_vector(31 downto 0);
|
intr_signal : in std_logic;
|
intr_signal : in std_logic;
|
| Line 361... |
Line 327... |
pipeline_stages : natural := 2); --2 or 3
|
pipeline_stages : natural := 2); --2 or 3
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
intr_in : in std_logic;
|
intr_in : in std_logic;
|
|
|
mem_address : out std_logic_vector(31 downto 0);
|
address_next : out std_logic_vector(31 downto 2); --for synch ram
|
mem_data_w : out std_logic_vector(31 downto 0);
|
byte_we_next : out std_logic_vector(3 downto 0);
|
mem_data_r : in std_logic_vector(31 downto 0);
|
|
mem_byte_we : out std_logic_vector(3 downto 0);
|
address : out std_logic_vector(31 downto 2);
|
|
byte_we : out std_logic_vector(3 downto 0);
|
|
data_w : out std_logic_vector(31 downto 0);
|
|
data_r : in std_logic_vector(31 downto 0);
|
mem_pause : in std_logic);
|
mem_pause : in std_logic);
|
end component;
|
end component;
|
|
|
component ram
|
component ram
|
generic(memory_type : string := "DEFAULT");
|
generic(memory_type : string := "DEFAULT");
|
| Line 378... |
Line 347... |
address : in std_logic_vector(31 downto 2);
|
address : in std_logic_vector(31 downto 2);
|
data_write : in std_logic_vector(31 downto 0);
|
data_write : in std_logic_vector(31 downto 0);
|
data_read : out std_logic_vector(31 downto 0));
|
data_read : out std_logic_vector(31 downto 0));
|
end component; --ram
|
end component; --ram
|
|
|
|
component ddr_ctrl
|
|
port(clk : in std_logic;
|
|
clk_2x : in std_logic;
|
|
reset_in : in std_logic;
|
|
|
|
address : in std_logic_vector(25 downto 2);
|
|
byte_we : in std_logic_vector(3 downto 0);
|
|
data_w : in std_logic_vector(31 downto 0);
|
|
data_r : out std_logic_vector(31 downto 0);
|
|
active : in std_logic;
|
|
pause : out std_logic;
|
|
|
|
SD_CK_P : out std_logic; --clock_positive
|
|
SD_CK_N : out std_logic; --clock_negative
|
|
SD_CKE : out std_logic; --clock_enable
|
|
|
|
SD_BA : out std_logic_vector(1 downto 0); --bank_address
|
|
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
|
|
SD_CS : out std_logic; --chip_select
|
|
SD_RAS : out std_logic; --row_address_strobe
|
|
SD_CAS : out std_logic; --column_address_strobe
|
|
SD_WE : out std_logic; --write_enable
|
|
|
|
SD_DQ : inout std_logic_vector(15 downto 0); --data
|
|
SD_UDM : out std_logic; --upper_byte_enable
|
|
SD_UDQS : inout std_logic; --upper_data_strobe
|
|
SD_LDM : out std_logic; --low_byte_enable
|
|
SD_LDQS : inout std_logic); --low_data_strobe
|
|
end component; --ddr
|
|
|
component uart
|
component uart
|
generic(log_file : string := "UNUSED");
|
generic(log_file : string := "UNUSED");
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
enable_read : in std_logic;
|
enable_read : in std_logic;
|
| Line 401... |
Line 400... |
reset : in std_logic;
|
reset : in std_logic;
|
uart_write : out std_logic;
|
uart_write : out std_logic;
|
uart_read : in std_logic;
|
uart_read : in std_logic;
|
|
|
address : out std_logic_vector(31 downto 2);
|
address : out std_logic_vector(31 downto 2);
|
|
byte_we : out std_logic_vector(3 downto 0);
|
data_write : out std_logic_vector(31 downto 0);
|
data_write : out std_logic_vector(31 downto 0);
|
data_read : in std_logic_vector(31 downto 0);
|
data_read : in std_logic_vector(31 downto 0);
|
write_byte_enable : out std_logic_vector(3 downto 0);
|
|
mem_pause_in : in std_logic;
|
mem_pause_in : in std_logic;
|
|
|
gpio0_out : out std_logic_vector(31 downto 0);
|
gpio0_out : out std_logic_vector(31 downto 0);
|
gpioA_in : in std_logic_vector(31 downto 0));
|
gpioA_in : in std_logic_vector(31 downto 0));
|
end component; --plasma
|
end component; --plasma
|
