Line 347... |
Line 347... |
address : in std_logic_vector(31 downto 2);
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address : in std_logic_vector(31 downto 2);
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data_write : in std_logic_vector(31 downto 0);
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data_write : in std_logic_vector(31 downto 0);
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data_read : out std_logic_vector(31 downto 0));
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data_read : out std_logic_vector(31 downto 0));
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end component; --ram
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end component; --ram
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component ddr_ctrl
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port(clk : in std_logic;
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clk_2x : in std_logic;
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reset_in : in std_logic;
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address : in std_logic_vector(25 downto 2);
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byte_we : in std_logic_vector(3 downto 0);
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data_w : in std_logic_vector(31 downto 0);
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data_r : out std_logic_vector(31 downto 0);
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active : in std_logic;
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pause : out std_logic;
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SD_CK_P : out std_logic; --clock_positive
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SD_CK_N : out std_logic; --clock_negative
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SD_CKE : out std_logic; --clock_enable
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SD_BA : out std_logic_vector(1 downto 0); --bank_address
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SD_A : out std_logic_vector(12 downto 0); --address(row or col)
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SD_CS : out std_logic; --chip_select
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SD_RAS : out std_logic; --row_address_strobe
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SD_CAS : out std_logic; --column_address_strobe
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SD_WE : out std_logic; --write_enable
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SD_DQ : inout std_logic_vector(15 downto 0); --data
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SD_UDM : out std_logic; --upper_byte_enable
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SD_UDQS : inout std_logic; --upper_data_strobe
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SD_LDM : out std_logic; --low_byte_enable
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SD_LDQS : inout std_logic); --low_data_strobe
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end component; --ddr
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component uart
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component uart
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generic(log_file : string := "UNUSED");
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generic(log_file : string := "UNUSED");
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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enable_read : in std_logic;
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enable_read : in std_logic;
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Line 391... |
Line 361... |
uart_write : out std_logic;
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uart_write : out std_logic;
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busy_write : out std_logic;
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busy_write : out std_logic;
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data_avail : out std_logic);
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data_avail : out std_logic);
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end component; --uart
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end component; --uart
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component eth_dma
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port(clk : in std_logic; --25 MHz
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reset : in std_logic;
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enable_eth : in std_logic;
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select_eth : in std_logic;
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rec_isr : out std_logic;
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send_isr : out std_logic;
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address : out std_logic_vector(31 downto 2); --to DDR
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byte_we : out std_logic_vector(3 downto 0);
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data_write : out std_logic_vector(31 downto 0);
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data_read : in std_logic_vector(31 downto 0);
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pause_in : in std_logic;
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mem_address : in std_logic_vector(31 downto 2); --from CPU
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mem_byte_we : in std_logic_vector(3 downto 0);
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data_w : in std_logic_vector(31 downto 0);
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pause_out : out std_logic;
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E_RX_CLK : in std_logic; --2.5 MHz receive
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E_RX_DV : in std_logic; --data valid
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E_RXD : in std_logic_vector(3 downto 0); --receive nibble
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E_TX_CLK : in std_logic; --2.5 MHz transmit
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E_TX_EN : out std_logic; --transmit enable
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E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
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end component; --eth_dma
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component plasma
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component plasma
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generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
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generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
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log_file : string := "UNUSED");
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log_file : string := "UNUSED";
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ethernet : std_logic := '0');
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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uart_write : out std_logic;
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uart_write : out std_logic;
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uart_read : in std_logic;
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uart_read : in std_logic;
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Line 409... |
Line 407... |
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gpio0_out : out std_logic_vector(31 downto 0);
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gpio0_out : out std_logic_vector(31 downto 0);
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gpioA_in : in std_logic_vector(31 downto 0));
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gpioA_in : in std_logic_vector(31 downto 0));
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end component; --plasma
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end component; --plasma
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component ddr_ctrl
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port(clk : in std_logic;
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clk_2x : in std_logic;
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reset_in : in std_logic;
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address : in std_logic_vector(25 downto 2);
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byte_we : in std_logic_vector(3 downto 0);
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data_w : in std_logic_vector(31 downto 0);
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data_r : out std_logic_vector(31 downto 0);
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active : in std_logic;
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pause : out std_logic;
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SD_CK_P : out std_logic; --clock_positive
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SD_CK_N : out std_logic; --clock_negative
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SD_CKE : out std_logic; --clock_enable
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SD_BA : out std_logic_vector(1 downto 0); --bank_address
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SD_A : out std_logic_vector(12 downto 0); --address(row or col)
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SD_CS : out std_logic; --chip_select
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SD_RAS : out std_logic; --row_address_strobe
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SD_CAS : out std_logic; --column_address_strobe
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SD_WE : out std_logic; --write_enable
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SD_DQ : inout std_logic_vector(15 downto 0); --data
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SD_UDM : out std_logic; --upper_byte_enable
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SD_UDQS : inout std_logic; --upper_data_strobe
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SD_LDM : out std_logic; --low_byte_enable
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SD_LDQS : inout std_logic); --low_data_strobe
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end component; --ddr
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end; --package mlite_pack
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end; --package mlite_pack
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package body mlite_pack is
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package body mlite_pack is
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