| Line 344... |
Line 344... |
data_w : out std_logic_vector(31 downto 0);
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data_w : out std_logic_vector(31 downto 0);
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data_r : in std_logic_vector(31 downto 0);
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data_r : in std_logic_vector(31 downto 0);
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mem_pause : in std_logic);
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mem_pause : in std_logic);
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end component;
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end component;
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component cache
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generic(memory_type : string := "DEFAULT");
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|
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port(clk : in std_logic;
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reset : in std_logic;
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address_next : in std_logic_vector(31 downto 2);
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byte_we_next : in std_logic_vector(3 downto 0);
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cpu_address : in std_logic_vector(31 downto 2);
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mem_busy : in std_logic;
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|
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cache_check : out std_logic; --Stage1: address_next in first 2MB DDR
|
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cache_checking : out std_logic; --Stage2: cache checking
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cache_miss : out std_logic); --Stage2-3: cache miss
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end component; --cache
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|
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component ram
|
component ram
|
generic(memory_type : string := "DEFAULT");
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generic(memory_type : string := "DEFAULT");
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port(clk : in std_logic;
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port(clk : in std_logic;
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enable : in std_logic;
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enable : in std_logic;
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write_byte_enable : in std_logic_vector(3 downto 0);
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write_byte_enable : in std_logic_vector(3 downto 0);
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| Line 398... |
Line 413... |
end component; --eth_dma
|
end component; --eth_dma
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|
|
component plasma
|
component plasma
|
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
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generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
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log_file : string := "UNUSED";
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log_file : string := "UNUSED";
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ethernet : std_logic := '0');
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ethernet : std_logic := '0';
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use_cache : std_logic := '0');
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port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset : in std_logic;
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reset : in std_logic;
|
uart_write : out std_logic;
|
uart_write : out std_logic;
|
uart_read : in std_logic;
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uart_read : in std_logic;
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|
|
address : out std_logic_vector(31 downto 2);
|
address : out std_logic_vector(31 downto 2);
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byte_we : out std_logic_vector(3 downto 0);
|
byte_we : out std_logic_vector(3 downto 0);
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data_write : out std_logic_vector(31 downto 0);
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data_write : out std_logic_vector(31 downto 0);
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data_read : in std_logic_vector(31 downto 0);
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data_read : in std_logic_vector(31 downto 0);
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mem_pause_in : in std_logic;
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mem_pause_in : in std_logic;
|
|
no_ddr_start : out std_logic;
|
|
no_ddr_stop : out std_logic;
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|
|
gpio0_out : out std_logic_vector(31 downto 0);
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gpio0_out : out std_logic_vector(31 downto 0);
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gpioA_in : in std_logic_vector(31 downto 0));
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gpioA_in : in std_logic_vector(31 downto 0));
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end component; --plasma
|
end component; --plasma
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|
| Line 424... |
Line 442... |
address : in std_logic_vector(25 downto 2);
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address : in std_logic_vector(25 downto 2);
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byte_we : in std_logic_vector(3 downto 0);
|
byte_we : in std_logic_vector(3 downto 0);
|
data_w : in std_logic_vector(31 downto 0);
|
data_w : in std_logic_vector(31 downto 0);
|
data_r : out std_logic_vector(31 downto 0);
|
data_r : out std_logic_vector(31 downto 0);
|
active : in std_logic;
|
active : in std_logic;
|
|
no_start : in std_logic;
|
|
no_stop : in std_logic;
|
pause : out std_logic;
|
pause : out std_logic;
|
|
|
SD_CK_P : out std_logic; --clock_positive
|
SD_CK_P : out std_logic; --clock_positive
|
SD_CK_N : out std_logic; --clock_negative
|
SD_CK_N : out std_logic; --clock_negative
|
SD_CKE : out std_logic; --clock_enable
|
SD_CKE : out std_logic; --clock_enable
|
