| Line 124... |
Line 124... |
constant mem_write8 : mem_source_type := "1101";
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constant mem_write8 : mem_source_type := "1101";
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function bv_to_integer(bv: in std_logic_vector) return integer;
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function bv_to_integer(bv: in std_logic_vector) return integer;
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function bv_adder(a : in std_logic_vector(32 downto 0);
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function bv_adder(a : in std_logic_vector(32 downto 0);
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b : in std_logic_vector(32 downto 0);
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b : in std_logic_vector(32 downto 0);
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do_sub: in std_logic) return std_logic_vector;
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do_add: in std_logic) return std_logic_vector;
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function bv_adder_lookahead(
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function bv_adder_lookahead(
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a : in std_logic_vector(32 downto 0);
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a : in std_logic_vector(32 downto 0);
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b : in std_logic_vector(32 downto 0);
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b : in std_logic_vector(32 downto 0);
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do_sub: in std_logic) return std_logic_vector;
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do_add: in std_logic) return std_logic_vector;
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function bv_negate(a : in std_logic_vector) return std_logic_vector;
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function bv_negate(a : in std_logic_vector) return std_logic_vector;
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function bv_increment(a : in std_logic_vector(31 downto 2)
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function bv_increment(a : in std_logic_vector(31 downto 2)
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) return std_logic_vector;
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) return std_logic_vector;
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function bv_inc6(a : in std_logic_vector
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function bv_inc6(a : in std_logic_vector
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) return std_logic_vector;
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) return std_logic_vector;
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-- For Altera
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COMPONENT lpm_add_sub
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GENERIC (
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lpm_width : NATURAL;
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lpm_direction : STRING;
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lpm_type : STRING;
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lpm_hint : STRING);
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PORT (
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dataa : IN STD_LOGIC_VECTOR (32 DOWNTO 0);
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add_sub : IN STD_LOGIC ;
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datab : IN STD_LOGIC_VECTOR (32 DOWNTO 0);
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result : OUT STD_LOGIC_VECTOR (32 DOWNTO 0));
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END COMPONENT;
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-- For Altera
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COMPONENT lpm_ram_dp
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GENERIC (
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lpm_width : NATURAL;
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lpm_widthad : NATURAL;
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rden_used : STRING;
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intended_device_family : STRING;
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lpm_indata : STRING;
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lpm_wraddress_control : STRING;
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lpm_rdaddress_control : STRING;
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lpm_outdata : STRING;
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use_eab : STRING;
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lpm_type : STRING);
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PORT (
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wren : IN STD_LOGIC ;
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wrclock : IN STD_LOGIC ;
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q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
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wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0));
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END COMPONENT;
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-- For Altera
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component lpm_ram_io
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GENERIC (
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intended_device_family : string;
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lpm_width : natural;
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lpm_widthad : natural;
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lpm_indata : string := "REGISTERED";
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lpm_address_control : string := "UNREGISTERED";
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lpm_outdata : string := "UNREGISTERED";
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lpm_file : string := "code.hex";
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use_eab : string := "ON";
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lpm_type : string := "LPM_RAM_DQ");
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PORT (
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outenab : in std_logic;
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address : in std_logic_vector(lpm_widthad-1 downto 0);
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inclock : in std_logic;
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we : in std_logic;
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dio : inout std_logic_vector(lpm_width-1 downto 0));
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end component; --lpm_ram_io
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-- For Xilinx
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component ramb4_s16_s16
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port (
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clka : in std_logic;
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rsta : in std_logic;
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addra : in std_logic_vector;
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dia : in std_logic_vector;
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ena : in std_logic;
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wea : in std_logic;
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doa : out std_logic_vector;
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clkb : in std_logic;
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rstb : in std_logic;
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addrb : in std_logic_vector;
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dib : in std_logic_vector;
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enb : in std_logic;
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web : in std_logic);
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end component;
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component pc_next
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port(clk : in std_logic;
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reset_in : in std_logic;
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pc_new : in std_logic_vector(31 downto 2);
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take_branch : in std_logic;
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pause_in : in std_logic;
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opcode25_0 : in std_logic_vector(25 downto 0);
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pc_source : in pc_source_type;
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pc_out : out std_logic_vector(31 downto 0);
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pc_out_plus4 : out std_logic_vector(31 downto 0));
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end component;
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component mem_ctrl
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port(clk : in std_logic;
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reset_in : in std_logic;
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pause_in : in std_logic;
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nullify_op : in std_logic;
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address_pc : in std_logic_vector(31 downto 0);
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opcode_out : out std_logic_vector(31 downto 0);
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address_data : in std_logic_vector(31 downto 0);
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mem_source : in mem_source_type;
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data_write : in std_logic_vector(31 downto 0);
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data_read : out std_logic_vector(31 downto 0);
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pause_out : out std_logic;
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|
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mem_address : out std_logic_vector(31 downto 0);
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mem_data_w : out std_logic_vector(31 downto 0);
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mem_data_r : in std_logic_vector(31 downto 0);
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mem_byte_sel : out std_logic_vector(3 downto 0);
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mem_write : out std_logic;
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mem_pause : in std_logic);
|
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end component;
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component control
|
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port(opcode : in std_logic_vector(31 downto 0);
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intr_signal : in std_logic;
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pause_in : in std_logic;
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rs_index : out std_logic_vector(5 downto 0);
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rt_index : out std_logic_vector(5 downto 0);
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rd_index : out std_logic_vector(5 downto 0);
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imm_out : out std_logic_vector(15 downto 0);
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alu_func : out alu_function_type;
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shift_func : out shift_function_type;
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mult_func : out mult_function_type;
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branch_func : out branch_function_type;
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a_source_out : out a_source_type;
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b_source_out : out b_source_type;
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c_source_out : out c_source_type;
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pc_source_out: out pc_source_type;
|
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mem_source_out:out mem_source_type);
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end component;
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|
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component reg_bank
|
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generic(memory_type : string := "TRI_PORT");
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port(clk : in std_logic;
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reset_in : in std_logic;
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rs_index : in std_logic_vector(5 downto 0);
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rt_index : in std_logic_vector(5 downto 0);
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rd_index : in std_logic_vector(5 downto 0);
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reg_source_out : out std_logic_vector(31 downto 0);
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reg_target_out : out std_logic_vector(31 downto 0);
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reg_dest_new : in std_logic_vector(31 downto 0);
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intr_enable : out std_logic);
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end component;
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component bus_mux
|
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port(imm_in : in std_logic_vector(15 downto 0);
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reg_source : in std_logic_vector(31 downto 0);
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a_mux : in a_source_type;
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a_out : out std_logic_vector(31 downto 0);
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|
|
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reg_target : in std_logic_vector(31 downto 0);
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b_mux : in b_source_type;
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|
b_out : out std_logic_vector(31 downto 0);
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c_bus : in std_logic_vector(31 downto 0);
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c_memory : in std_logic_vector(31 downto 0);
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c_pc : in std_logic_vector(31 downto 0);
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c_pc_plus4 : in std_logic_vector(31 downto 0);
|
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c_mux : in c_source_type;
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reg_dest_out : out std_logic_vector(31 downto 0);
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|
|
|
branch_func : in branch_function_type;
|
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take_branch : out std_logic);
|
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end component;
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|
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component alu
|
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generic(adder_type : string := "GENERIC");
|
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port(a_in : in std_logic_vector(31 downto 0);
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b_in : in std_logic_vector(31 downto 0);
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alu_function : in alu_function_type;
|
|
c_alu : out std_logic_vector(31 downto 0));
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end component;
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|
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component shifter
|
|
port(value : in std_logic_vector(31 downto 0);
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shift_amount : in std_logic_vector(4 downto 0);
|
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shift_func : in shift_function_type;
|
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c_shift : out std_logic_vector(31 downto 0));
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end component;
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component mult
|
|
generic(adder_type : string := "GENERIC");
|
|
port(clk : in std_logic;
|
|
a, b : in std_logic_vector(31 downto 0);
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mult_func : in mult_function_type;
|
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c_mult : out std_logic_vector(31 downto 0);
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pause_out : out std_logic);
|
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end component;
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|
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component mlite_cpu
|
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generic(memory_type : string := "ALTERA");
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port(clk : in std_logic;
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reset_in : in std_logic;
|
|
intr_in : in std_logic;
|
|
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mem_address : out std_logic_vector(31 downto 0);
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mem_data_w : out std_logic_vector(31 downto 0);
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mem_data_r : in std_logic_vector(31 downto 0);
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mem_byte_sel: out std_logic_vector(3 downto 0);
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mem_write : out std_logic;
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mem_pause : in std_logic);
|
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end component;
|
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-- For test bench (not synthesizable)
|
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component ram
|
|
generic(load_file_name : string);
|
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port(clk : in std_logic;
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mem_byte_sel : in std_logic_vector(3 downto 0);
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mem_write : in std_logic;
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mem_address : in std_logic_vector;
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mem_data_w : in std_logic_vector(31 downto 0);
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mem_data_r : out std_logic_vector(31 downto 0));
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end component; --ram
|
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|
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component uart
|
|
generic(save_file_name : string := "UNUSED");
|
|
port(clk : in std_logic;
|
|
reset : in std_logic;
|
|
uart_sel : in std_logic;
|
|
data : in std_logic_vector(7 downto 0);
|
|
read_pin : in std_logic;
|
|
write_pin : out std_logic;
|
|
pause : out std_logic);
|
|
end component; --uart
|
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end; --package mlite_pack
|
end; --package mlite_pack
|
|
|
package body mlite_pack is
|
package body mlite_pack is
|
|
|
function add_1(a:integer) return integer is
|
function add_1(a:integer) return integer is
|
| Line 162... |
Line 385... |
return result;
|
return result;
|
end; --function bv_to_integer
|
end; --function bv_to_integer
|
|
|
function bv_adder(a : in std_logic_vector(32 downto 0);
|
function bv_adder(a : in std_logic_vector(32 downto 0);
|
b : in std_logic_vector(32 downto 0);
|
b : in std_logic_vector(32 downto 0);
|
do_sub: in std_logic) return std_logic_vector is
|
do_add: in std_logic) return std_logic_vector is
|
variable carry_in : std_logic;
|
variable carry_in : std_logic;
|
variable bb : std_logic_vector(32 downto 0);
|
variable bb : std_logic_vector(32 downto 0);
|
variable result : std_logic_vector(32 downto 0);
|
variable result : std_logic_vector(32 downto 0);
|
begin
|
begin
|
result := "000000000000000000000000000000000";
|
result := '0' & ZERO;
|
if do_sub = '0' then
|
if do_add = '1' then
|
bb := b;
|
bb := b;
|
carry_in := '0';
|
carry_in := '0';
|
else
|
else
|
bb := not b;
|
bb := not b;
|
carry_in := '1';
|
carry_in := '1';
|
| Line 186... |
Line 409... |
end; --function
|
end; --function
|
|
|
function bv_adder_lookahead(
|
function bv_adder_lookahead(
|
a : in std_logic_vector(32 downto 0);
|
a : in std_logic_vector(32 downto 0);
|
b : in std_logic_vector(32 downto 0);
|
b : in std_logic_vector(32 downto 0);
|
do_sub: in std_logic) return std_logic_vector is
|
do_add: in std_logic) return std_logic_vector is
|
variable carry : std_logic_vector(32 downto 0);
|
variable carry : std_logic_vector(32 downto 0);
|
variable p, g : std_logic_vector(32 downto 0);
|
variable p, g : std_logic_vector(32 downto 0);
|
variable bb : std_logic_vector(32 downto 0);
|
variable bb : std_logic_vector(32 downto 0);
|
variable result : std_logic_vector(32 downto 0);
|
variable result : std_logic_vector(32 downto 0);
|
variable i : natural;
|
variable i : natural;
|
begin
|
begin
|
carry := "000000000000000000000000000000000";
|
carry := '0' & ZERO;
|
if do_sub = '0' then
|
if do_add = '1' then
|
bb := b;
|
bb := b;
|
carry(0) := '0';
|
carry(0) := '0';
|
else
|
else
|
bb := not b;
|
bb := not b;
|
carry(0) := '1';
|
carry(0) := '1';
|
| Line 249... |
Line 472... |
function bv_increment(a : in std_logic_vector(31 downto 2)
|
function bv_increment(a : in std_logic_vector(31 downto 2)
|
) return std_logic_vector is
|
) return std_logic_vector is
|
variable carry_in : std_logic;
|
variable carry_in : std_logic;
|
variable result : std_logic_vector(31 downto 2);
|
variable result : std_logic_vector(31 downto 2);
|
begin
|
begin
|
result := "000000000000000000000000000000";
|
result := ZERO(31 downto 2);
|
carry_in := '1';
|
carry_in := '1';
|
for index in 2 to 31 loop
|
for index in 2 to 31 loop
|
result(index) := a(index) xor carry_in;
|
result(index) := a(index) xor carry_in;
|
carry_in := a(index) and carry_in;
|
carry_in := a(index) and carry_in;
|
end loop;
|
end loop;
|
